Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
To facilitate consideration of any amendment that may be presented in response to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application that clearly support the amendment.
DETAIL ACTION
Election/Restrictions
Applicant's Election without traverse of Group I (claims 1-9 and 14-17) in the reply filed on 8/04/25 is acknowledged.
Claims 10-13 and 18-20 have been canceled by this election.
Therefore, claims 1-9 and 14-17 are now pending in this application. Claims 1 and 14 are independent.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 3/26/25 by the applicant have been received and fully considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
The terms “resistance state level with the highest stability” and “lowest stability” (claims 2–4, 5–7, 9, 12–14, 15–17, 19) are indefinite because “stability” lacks a defined metric. It is unclear whether it refers to retention time, endurance, drift, or variability. Clarification is needed,
The phrase “appearance rate” (claims 1–8, 11–18) is indefinite, as it could mean frequency in training data, runtime occurrence, or statistical representation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Linderman (US 9152827) in view of Su (US 12112825), and further in view of Miller (US 2011/0303354).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1,
(Recited) An apparatus, comprising: a plurality of bit lines intersecting with a plurality of word lines; a plurality of cross-point devices, wherein each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines, and wherein each of the plurality of cross-point devices comprises a resistive random-access memory (RRAM) device; and a plurality of switches connected to the plurality of word lines, wherein each of the plurality of switches is selectively connected to ground or a reference voltage.
Linderman discloses a computing cross-point memristor array including word lines (WLs) intersecting bit lines (BLs), with RRAM devices at each intersection (Fig. 1–2; col. 3:1-18; col. 5:5-30). Linderman further discloses per-line gating and drive circuits to bias selected WL/BL pairs during read/program operations (Fig. 4; col. 7:4-34), and selector transistors used to isolate WLs/BLs during read operations (col. 8:1-14).
Linderman does not explicitly show each WL having a switch that selectively connects the WL to ground or a reference voltage for bit-serial input.
Su teaches programmable WL bias control for RRAM, where each WL is selectively coupled to ground or Vref during read/program sequences via a switching circuit (Fig. 5A–5C; col. 8:7-45, col. 9:1-26). Su explicitly provides WL control logic to toggle between bias rails and ground.
A person ordinary in the art would combine Su’s WL bias switching scheme with Linderman’s cross-point array to achieve improved bias integrity and easier bit-serial connectivity. Both references solve the same problem: accurate WL control to reduce sneak current and support incremental read/program cycles.
Thus, it would have been obvious to apply Su’s WL switching to Linderman’s array to achieve the claimed configuration shown above.
As for claim 2, WL grounded for first bit
Linderman teaches WL bias sequencing. Su teaches WL switching to ground. Using ground for logical “1” detection in serial input is a predictable usage of Su’s ground-drive circuitry (col. 8:10-41).
Claim 2 rejected over Linderman + Su.
As for claim 3 – WL to Vref for second bit
Su discloses WL switching to Vref during read or write (col. 8:35-45).
Mapping “bit-0” to Vref is a straightforward adaptation.
Claim 3 rejected over Linderman + Su.
As for claim 4 – “bit-1 = ground, bit-0 = reference”
Su shows switching logic to choose WL polarity and voltage (col. 9:1-25).
Assigning bit values to WL voltage polarity is a trivial logic-mapping design choice.
Claim 4 rejected over Linderman + Su.
As for claim 5 – RRAM terminal to WL, other to source/drain of transistor
Linderman shows RRAM between WL and a transistor-connected BL driver (Fig. 4; col. 7:3-23).
Su also uses WL-side RRAM with transistor-based drive.
Claim 5 rejected over Linderman + Su.
As for claim 6– Vref corresponds to read voltage
Linderman associates bias voltage with read reference (col. 5:15-27).
Su also uses WL Vread (col. 9:1-15).
Claim 6 rejected over Linderman + Su.
As for claim 7 – buffer generates reference voltage
Miller teaches reference-voltage buffer and distribution network for sensing in cross-point NVM (Fig. 4; ¶[0047]-[0055]).
Claim 7 rejected over Linderman + Su + Miller.
As for claim 8 – unity-gain amplifier buffer
Miller explicitly teaches unity-gain amplifier for WL reference buffering (¶[0053]).
Claim 8 rejected over Linderman + Su + Miller.
As for claim 9 – switches include multiplexers
Su discloses WL selection switches and decoder-based multiplexing (col. 9:5-32).
Miller uses multiplexed sense and reference paths (¶[0049]).
Claim 9 rejected over Linderman + Su (+ Miller support).
Regarding independent claim 14
(Recited) 14. (Original) An apparatus, comprising: a first plurality of bit lines and a second plurality of bit lines intersecting with a plurality of word lines; a first switch that selectively connects a first segment of a first word line of the plurality of word lines to ground; a second switch that selectively connects a second segment of the first word line to ground; a first plurality of cross-point devices connecting to the first segment of the first word line and the first plurality of bit lines; and a second plurality of cross-point devices connecting to the second segment of the first word line and the second plurality of bit lines.
Linderman ’827 disclose WL/BL network with segment-level access devices (col. 7:5-28) and RRAM array partitioning and peripheral isolation logic (Fig. 4).
Linderman does not explicit disclose WL segmentation into first & second WL segments each separately grounded.
Su ’825 teaches Per-WL-segment bias control, multi-segment WL gating (col. 9:6-33; Fig. 7). Su teaches isolating WL segments to reduce coupling and sneak paths.
Thus, it would have been obvious to apply Su’s segmenting WLs and independently grounding them to reduce leakage and mirror tile-wise compute architectures.
Claim 14 rejected over Linderman + Su. WL switching to Linderman’s array to achieve the claimed configuration shown in claim 14 above.
As for claim 15 – RRAM in each segment
Linderman teaches identical array blocks across segments.
RRAM in both parts is inherent.
As for claim 16 – first segment floating when switch off
Su teaches floating isolated WL segments (col. 9:6-20).
As for claim 17 – second segment floating when switch off
Same reasoning as claim 16; Su teaches floating unselected WL segments.
Citation of Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
Conclusion
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HIEN N. NGUYEN
Primary Examiner
Art Unit 2824
/HN/
October 28, 2025
/HIEN N NGUYEN/Primary Examiner, Art Unit 2824