DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention of Group I, Claims 11-20, in the reply filed on 02/26/2026 is acknowledged.
Claims 21-29 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/26/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-14 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hua et al. (US 2020/0286958).
Regarding claim 11, Hua et al. discloses, as shown in Figures 4-5L, a semiconductor device comprising:
a memory stack layer (528) that comprises at least one gate layer (530) and at least one gate dielectric layer (508/532) disposed alternately along a first direction (z direction);
memory channel structures (516) penetrating through the memory stack layer along the first direction;
a top selective gate layer (550,ILD) disposed on a side of the memory stack layer in the first direction; and
top selective gate cut lines (portion of 550) penetrating through at least part of the top selective gate layer along the first direction, wherein sizes of bottoms of the top selective gate cut lines close to the memory stack layer in a second direction (x/y direction) are greater than sizes of tops of the top selective gate cut lines far away from the memory stack layer in the second direction, and the first direction intersects the second direction.
[AltContent: textbox (gate line slit top insulation portion)][AltContent: textbox (top selective gate cut line)][AltContent: arrow]
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Regarding claim 12, Hua et al. discloses the device further comprising:
gate line slit top insulation portions (other portion of 550) penetrating through at least part of the top selective gate layer along the first direction, wherein the gate line slit top insulation portions and the top selective gate cut lines are disposed as being spaced apart along the second direction, and sizes of bottoms of the gate line slit top insulation portions close to the memory stack layer in the second direction are greater than sizes of tops of the gate line slit top insulation portions far away from the memory stack layer in the second direction (see Fig. 5L above).
Regarding claim 13, Hua et al. discloses sizes of the gate line slit top insulation portions along the second direction are greater than sizes of the top selective gate cut lines along the second direction (see Fig. 5L above).
Regarding claim 14, Hua et al. discloses the device further comprising:
a first isolation layer (uppermost 508,532), wherein at least part of the first isolation layer is located between the top selective gate cut lines as well as the gate line slit top insulation portions and the memory stack layer in the first direction, and a material of the first isolation layer [0051] is different from a material of the top selective gate cut lines (portion of 550, ILD, [0041]).
Regarding claim 19, Hua et al. discloses the first isolation layer includes at least one of a carbon-doped silicon nitride layer, a silicon oxynitride layer, a silicon nitride layer, and a stack of a silicon oxide layer and a silicon nitride layer [0051], [0058].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hua et al. (US 2020/0286958) in view of Higashi et al. (US 2018/0261623).
Hua et al. discloses, as shown in Figures 4-5L, a memory comprising:
a semiconductor device comprising:
a memory stack layer (528) that comprises at least one gate layer (530) and at least one gate dielectric layer (508/532) disposed alternately along a first direction (z direction);
memory channel structures (516) penetrating through the memory stack layer along the first direction;
a top selective gate layer (550) disposed on a side of the memory stack layer in the first direction; and
top selective gate cut lines (portion of 550 memory stack 528) penetrating through at least part of the top selective gate layer along the first direction, wherein sizes of bottoms of the top selective gate cut lines close to the memory stack layer in a second direction are greater than sizes of tops of the top selective gate cut lines far away from the memory stack layer in the second direction, and the first direction intersects the second direction.
Hua et al. does not disclose a memory is integrated into a memory system that comprising a controller which is connected with the memory and configured to control the memory. However, Higashi et al. discloses a memory system comprising a memory (memory cell array) and a controller (memory controller) connected with the memory. Note Figure 14 of Higashi et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form to integrate the memory of Hua et al. into a memory system which comprising a controller, such as taught by Higashi et al. in order to control the memory to perform the desired function.
Allowable Subject Matter
Claims 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant' s claims 15-18 are allowable over the references of record because none of these references disclose or can be combined to yield the claimed first isolation layer is further located between the top selective gate layer and the memory stack layer; and the semiconductor device further comprises: top selective channel structures that penetrate through the top selective gate layer and the first isolation layer along the first direction and are connected with the memory channel structures, as recited in claim 15; the top selective gate layer further penetrates through the first isolation layer; and the semiconductor device further comprises a second isolation layer, wherein at least part of the second isolation layer is located between the top selective gate layer and the memory stack layer, as recited in claim 16; gate line slit structures penetrating through the gate line slit top insulation portions, the first isolation layer and the memory stack layer along the first direction, as recited in claim 18.
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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