Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's amendment/arguments filed on 4/9/26 as being acknowledged and entered. By this amendment claims 1-20 are pending and claims 17-20 are withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 11-12 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al. (US Patent 11,502,167).
Claim 1: Hong teaches (Fig. 6) an integrated circuit device comprising: an upper transistor structure on a substrate (605), the upper transistor structure comprising an upper channel region (620) and an upper gate electrode (625) on the upper channel region; a lower transistor structure between the substrate and the upper transistor structure in a vertical direction, the lower transistor structure comprising a lower channel region (610) and a lower gate electrode (615 around 610 and below/adjacent 630) on the lower channel region; and an intergate contact (615 above 630) between the lower gate electrode and the upper gate electrode in the vertical direction, wherein the lower gate electrode is electrically connected to the upper gate electrode through the intergate contact, and wherein a portion of a lower surface of the intergate contact protrudes beyond a side surface of the lower gate electrode (over 630), and wherein an uppermost surface of the upper gate electrode is farther from the substrate than an uppermost surface of the intergate contact in the vertical direction.
Claim 2: Hong teaches (Fig. 6) the lower channel region and the upper channel region are spaced apart from each other in a vertical direction, and the portion of the lower surface of the intergate contact protrudes beyond the side surface of the lower gate electrode in a horizontal direction.
Claim 3: Hong teaches (Fig. 6) the intergate contact is in contact with both the upper gate electrode and the lower gate electrode.
Claim 4: Hong teaches (Fig. 6) an upper surface (below 630) of the lower gate electrode has a first width that is narrower than a second width of the lower surface of the intergate contact.
Claim 5: Hong teaches (Fig. 6) an upper surface of the intergate contact has a third width that is wider than a fourth width of a lower surface of the upper gate electrode.
Claim 11: Hong teaches (Fig. 6) the upper channel region overlaps the lower channel region.
Claim 12: Hong teaches (Fig. 6) (see claim 1) an integrated circuit device comprising: an upper transistor structure on a substrate, the upper transistor structure comprising an upper channel region and an upper gate electrode on the upper channel region; a lower transistor structure between the substrate and the upper transistor structure in a vertical direction, the lower transistor structure comprising a lower channel region and a lower gate electrode on the lower channel region; and an intergate contact between the lower gate electrode and the upper gate electrode in the vertical direction, wherein the lower channel region and the upper channel region are spaced apart from each other in the vertical direction, wherein an uppermost surface of the intergate contact has a third width in a horizontal direction, and the third width is wider than a fourth width of an interface between the intergate contact and the upper gate electrode in the horizontal direction, and wherein an uppermost surface of the upper gate electrode is farther from the substrate than the uppermost surface of the intergate contact in the vertical direction. It is noted that the claim contains language pertaining to a third and fourth width but there is not first and second width until claim 15.
Claim 14: Hong teaches (Fig. 6) the upper gate electrode does not overlap an edge portion of the upper surface of the intergate contact in the vertical direction.
Claim 15: Hong teaches (Fig. 6) an upper surface of the lower gate electrode has a first width in the horizontal direction, a lower surface of the intergate contact has a second width in the horizontal direction, and the second width is wider than the first width.
Claim(s) 1-4, 10-12, and 14-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yun et al. (US PGPub 2023/0343824).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claim 1: Yun teaches (Fig. 15A-C, 16) an integrated circuit device comprising: an upper transistor structure on a substrate (305), the upper transistor structure comprising an upper channel region (320c) and an upper gate electrode (325M) on the upper channel region; a lower transistor structure between the substrate and the upper transistor structure in a vertical direction, the lower transistor structure comprising a lower channel region (310c) and a lower gate electrode (315M) on the lower channel region; and an intergate contact (340) between the lower gate electrode and the upper gate electrode in the vertical direction, wherein the lower gate electrode is electrically connected to the upper gate electrode through the intergate contact, and wherein a portion of a lower surface of the intergate contact protrudes beyond a side surface of the lower gate electrode, and wherein an uppermost surface of the upper gate electrode is farther from the substrate than an uppermost surface of the intergate contact in the vertical direction [0126].
Claim 2: Yun teaches (Fig. 15C) the lower channel region and the upper channel region are spaced apart from each other in a vertical direction, and the portion of the lower surface of the intergate contact protrudes beyond the side surface of the lower gate electrode in a horizontal direction.
Claim 3: Yun teaches (Fig. 15C, 16 (s360)) the intergate contact is in contact with both the upper gate electrode and the lower gate electrode.
Claim 4: Yun teaches (Fig. 15C) an upper surface of the lower gate electrode has a first width that is narrower than a second width of the lower surface of the intergate contact.
Claim 10: Yun teaches [0124-0126] the intergate contact comprises a material different from the upper gate electrode or the lower gate electrode.
Claim 11: Yun teaches (Fig. 15C) the upper channel region overlaps the lower channel region.
Claim 12: Yun teaches (Fig. 15A-C, 16) (see claim 1) an integrated circuit device comprising: an upper transistor structure on a substrate, the upper transistor structure comprising an upper channel region and an upper gate electrode on the upper channel region; a lower transistor structure between the substrate and the upper transistor structure in a vertical direction, the lower transistor structure comprising a lower channel region and a lower gate electrode on the lower channel region; and an intergate contact between the lower gate electrode and the upper gate electrode in the vertical direction, wherein the lower channel region and the upper channel region are spaced apart from each other in the vertical direction, wherein an uppermost surface of the intergate contact has a third width in a horizontal direction, and the third width is wider than a fourth width of an interface between the intergate contact and the upper gate electrode in the horizontal direction (Fig. 15B), and wherein an uppermost surface of the upper gate electrode is farther from the substrate than the uppermost surface of the intergate contact in the vertical direction. It is noted that the claim contains language pertaining to a third and fourth width but there is not first and second width until claim 15.
Claim 14: Yun teaches (Fig. 15B) the upper gate electrode does not overlap an edge portion of the upper surface of the intergate contact in the vertical direction.
Claim 15: Yun teaches (Fig. 15C) an upper surface of the lower gate electrode has a first width in the horizontal direction, a lower surface of the intergate contact has a second width in the horizontal direction, and the second width is wider than the first width.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (US Patent 11,502,167), as applied to claims 1 and 12 above, and further in view of Xie et al. (US PGPub 2023/0335585).
Regarding claim 8, as described above, Song substantially reads on the invention as claimed, except Song does not teach the lower transistor structure further comprises a lower gate spacer on the side surface of the lower gate electrode, and wherein the portion of the lower surface of the intergate contact is in contact with the lower gate spacer. Xie teaches the lower transistor structure further comprises a lower gate spacer (310) (Fig. 17) on the side surface of the lower gate electrode (910) (Fig. 23), and wherein the portion of the lower surface of the intergate contact (2530) is in contact with the lower gate spacer (Fig. 25) to form latch cross coupling transistor pairs which are common in the art of information storage [0002]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Song to have had the lower transistor structure further comprises a lower gate spacer on the side surface of the lower gate electrode, and wherein the portion of the lower surface of the intergate contact is in contact with the lower gate spacer to form latch cross coupling transistor pairs which are common in the art of information storage [0002] as taught by Xie.
Claim 9: Xie teaches (Fig. 25) the lower channel region and the upper channel region are spaced apart from each other in a vertical direction, the lower transistor structure further comprises a lower gate spacer (310) on the side surface of the lower gate electrode, and the upper transistor structure further comprises an upper gate spacer (1010) (Fig. 24) on a side surface of the upper gate electrode, and the side surface of the lower gate electrode and the side surface of the upper gate electrode face the same direction and are offset from each other in a horizontal direction.
Allowable Subject Matter
Claims 6-7, 13 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record does not teach the various requirements on widths of the intergate contact and the respective gate electrodes and interfaces. Additionally, for claim 16, the prior art does not teach an intergate insulator extending between the lower channel region and the upper channel region, wherein an edge portion of the upper surface of the intergate contact is in contact with the intergate insulator, and the upper gate electrode extends through the intergate insulator.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at 5712721705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SARAH K SALERNO/Primary Examiner, Art Unit 2814
Prosecution Insights