Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I Species II in the reply filed on 11/11/25 is acknowledged.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/11/25.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Song et al. (EP 4036959A2).
Claim 1: Song teaches (Fig. 2C) [0021-0036, 0074-0079] An integrated circuit device comprising: an upper transistor structure (210b, 220a) on a substrate, the upper transistor structure comprising an upper channel region (220a) and an upper gate electrode (210b) on the upper channel region; a lower transistor structure (210c, 220b) between the substrate and the upper transistor structure, the lower transistor structure comprising a lower channel region (220b) and a lower gate electrode (210c) on the lower channel region; and an intergate contact (240a-c) between the lower gate electrode and the upper gate electrode, wherein the lower gate electrode is electrically connected to the upper gate electrode through the intergate contact, and a portion of a lower surface of the intergate contact protrudes beyond a side surface of the lower gate electrode.
Claim 2: Song teaches (Fig. 2A-2C) the lower channel region and the upper channel region are spaced apart from each other in a vertical direction, and the portion of the lower surface of the intergate contact protrudes beyond the side surface of the lower gate electrode in a horizontal direction.
Claim 3: Song teaches (Fig. 2A-2C) the intergate contact is in contact with both the upper gate electrode and the lower gate electrode.
Claim 4: Song teaches (Fig. 2A-2C) an upper surface of the lower gate electrode has a first width that is narrower than a second width of the lower surface of the intergate contact.
Claim 5: Song teaches (Fig. 2A-2C) an upper surface of the intergate contact has a third width that is wider than a fourth width of a lower surface of the upper gate electrode.
Claim 7: Song teaches (Fig. 2A-2C) wherein a width of the intergate contact increases with increasing distance from the substrate.
Claim 11: Song teaches (Fig. 2A-2C) the upper channel region overlaps the lower channel region.
Claims 1-7, and 10-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Song et al. (EP 4135018 A1).
Claim 1: Song teaches (Fig. 3A-C) An integrated circuit device comprising: an upper transistor structure (UTS) on a substrate, the upper transistor structure comprising an upper channel region (315C) and an upper gate electrode (315G) on the upper channel region; a lower transistor structure (LTS) between the substrate and the upper transistor structure, the lower transistor structure comprising a lower channel region (305C) and a lower gate electrode (305G) on the lower channel region; and an intergate contact (320) between the lower gate electrode and the upper gate electrode, wherein the lower gate electrode is electrically connected to the upper gate electrode through the intergate contact, and a portion of a lower surface of the intergate contact protrudes beyond a side surface of the lower gate electrode.
Claim 2: Song teaches (Fig. 3A-C) the lower channel region and the upper channel region are spaced apart from each other in a vertical direction, and the portion of the lower surface of the intergate contact protrudes beyond the side surface of the lower gate electrode in a horizontal direction.
Claim 3: Song teaches (Fig. 3A-C) the intergate contact is in contact with both the upper gate electrode and the lower gate electrode.
Claim 4: Song teaches (Fig. 3A-C) an upper surface of the lower gate electrode has a first width that is narrower than a second width of the lower surface of the intergate contact.
Claim 5: Song teaches (Fig. 3A-C) an upper surface of the intergate contact has a third width that is wider than a fourth width of a lower surface of the upper gate electrode.
Claim 6: Song teaches (Fig. 3A-C) the third width is wider than the second width.
Claim 7: Song teaches (Fig. 3A-3C) wherein a width of the intergate contact increases with increasing distance from the substrate.
Claim 10: Song teaches [0032] the intergate contact comprises a material different from the upper gate electrode or the lower gate electrode.
Claim 11: Song teaches (Fig. 3A-3C) the upper channel region overlaps the lower channel region.
Claim 12: Song teaches (Fig. 3A-C) (see claim 1 for reference numbers) an integrated circuit device comprising: an upper transistor structure on a substrate, the upper transistor structure comprising an upper channel region and an upper gate electrode on the upper channel region; a lower transistor structure between the substrate and the upper transistor structure, the lower transistor structure comprising a lower channel region and a lower gate electrode on the lower channel region; and an intergate contact between the lower gate electrode and the upper gate electrode, wherein the lower channel region and the upper channel region are spaced apart from each other in a vertical direction, and wherein an upper surface of the intergate contact has a third width in a horizontal direction, and the third width is wider than a fourth width of an interface between the intergate contact and the upper gate electrode in the horizontal direction.
Claim 13: Song teaches (Fig. 3A-C) the intergate contact has a width in the horizontal direction increasing with increasing distance from the substrate.
Claim 14: Song teaches (Fig. 3A-C) the upper gate electrode does not overlap an edge portion of the upper surface of the intergate contact in the vertical direction.
Claim 15: Song teaches (Fig. 3A-C) an upper surface of the lower gate electrode has a first width in the horizontal direction, a lower surface of the intergate contact has a second width in the horizontal direction, and the second width is wider than the first width.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (EP 4135018 A1), as applied to claims 1 and 12 above, and further in view of Xie et al. (US PGPub 2023/0335585.
Regarding claim 8, as described above, Song substantially reads on the invention as claimed, except Song does not teach the lower transistor structure further comprises a lower gate spacer on the side surface of the lower gate electrode, and wherein the portion of the lower surface of the intergate contact is in contact with the lower gate spacer. Xie teaches the lower transistor structure further comprises a lower gate spacer (310) (Fig. 17) on the side surface of the lower gate electrode (910) (Fig. 23), and wherein the portion of the lower surface of the intergate contact (2530) is in contact with the lower gate spacer (Fig. 25) to form latch cross coupling transistor pairs which are common in the art of information storage [0002]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Song to have had the lower transistor structure further comprises a lower gate spacer on the side surface of the lower gate electrode, and wherein the portion of the lower surface of the intergate contact is in contact with the lower gate spacer to form latch cross coupling transistor pairs which are common in the art of information storage [0002] as taught by Xie.
Claim 9: Xie teaches (Fig. 25) the lower channel region and the upper channel region are spaced apart from each other in a vertical direction, the lower transistor structure further comprises a lower gate spacer (310) on the side surface of the lower gate electrode, and the upper transistor structure further comprises an upper gate spacer (1010) (Fig. 24) on a side surface of the upper gate electrode, and the side surface of the lower gate electrode and the side surface of the upper gate electrode face the same direction and are offset from each other in a horizontal direction.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record does not teach an intergate insulator extending between the lower channel region and the upper channel region, wherein an edge portion of the upper surface of the intergate contact is in contact with the intergate insulator, and the upper gate electrode extends through the intergate insulator.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814