Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-5, 7-8 in the reply filed on 2/2/26 is acknowledged. Claim 6 is withdrawn from further consideration by the examiner, 37 C.F.R. 1.142(b) as being drawn to a non-elected invention.
Information Disclosure Statement
The information disclosure statements filed 8/28/23 have been considered.
Oath/Declaration
Oath/Declaration filed on 8/28/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Nagaune (U.S. Patent Publication No. 2014/0048918).
Referring to figures 1-8, Nagaune teaches a semiconductor module, comprising:
a circuit board (4) includes a first conductive member (2a) and a second conductive member (2a) disposed thereon and a semiconductor element (3) mounted on the second conductive member (see figures 6a, 8a); and
a lead (7) electrically connecting the semiconductor element (3) to the first conductive member (2a), wherein
the lead (7) includes a first bonding portion bonded to the first conductive member via a bonding material and a coupling portion extending in a first direction from the first bonding portion (see figures 6a, 8a), and
the first bonding portion (7) has a first width end and a second width end that is opposite to the first width end and is connected to the coupling portion, and the lead has a first length side and a second length side opposite to each other in a second direction orthogonal to the first direction (see figures 6a, 8a),
the lead (7) has in the second direction, a first width at a first position and a second width at a second position, the first position being located in the bonding portion, the second position being located away from the first position in the first direction from the first width end toward the second width end (see figures 6a, 8a), and
in the plan view, the lead (7) has a shape in which the first width (73b, horizontal portion) is greater than the second width (73) such that positions of the first and second length sides at the second position are respectively located inward in the second direction with respect to positions of the first and second length sides at the first position (see figure 6a).
Regarding to claim 2, the first bonding portion of the lead (73b) has a rectangular shape in the plan view, and has the first width in the second direction, and the coupling portion has the second width in the second direction (see figures 6a, 8a).
Regarding to claim 5, the semiconductor element (3) includes an electrode (3a), the lead (73) further includes a second bonding portion bonded (73b) to the electrode (3a) of the semiconductor element (3) via a second bonding material (73a), and the coupling portion couples the first bonding portion (73a) and the second bonding portion (73b) to each other (see figure 6a, 8a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagaune (U.S. Patent Publication No. 2014/0048918) applied in claim(s) 1-2, 5 above in view of Kato et al. (U.S. Patent Publication No. 2019/0088575).
Referring to figures 1-8, Nagaune teaches a semiconductor module, comprising:
a circuit board (4) includes a first conductive member (2a) and a second conductive member (2a) disposed thereon and a semiconductor element (3) mounted on the second conductive member (see figures 6a, 8a); and
a lead (7) electrically connecting the semiconductor element (3) to the first conductive member (2a), wherein
the lead (7) includes a first bonding portion bonded to the first conductive member via a bonding material and a coupling portion extending in a first direction from the first bonding portion (see figures 6a, 8a), and
the first bonding portion (7) has a first width end and a second width end that is opposite to the first width end and is connected to the coupling portion, and the lead has a first length side and a second length side opposite to each other in a second direction orthogonal to the first direction (see figures 6a, 8a),
the lead (7) has in the second direction, a first width at a first position and a second width at a second position, the first position being located in the bonding portion, the second position being located away from the first position in the first direction from the first width end toward the second width end (see figures 6a, 8a), and
in the plan view, the lead (7) has a shape in which the first width (73b, horizontal portion) is greater than the second width (73) such that positions of the first and second length sides at the second position are respectively located inward in the second direction with respect to positions of the first and second length sides at the first position (see figure 6a).
However, the reference does not clearly teach a semiconductor device, a cooler disposed at a side of the circuit board opposite to a side of the circuit board where the semiconductor element is mounted (in claim 7) and a vehicle, comprising the semiconductor (in claim 8).
Nagaune teaches a semiconductor device, a cooler (11) disposed at a side of the circuit board (13) opposite to a side of the circuit board where the semiconductor element (14) is mounted (see paragraph# 27, figure 1, meeting claim 7) and a vehicle, comprising the semiconductor (see paragraph 6 meeting claim 8).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a cooler disposed at a side of the circuit board opposite to a side of the circuit board where the semiconductor element is mounted and a vehicle in Kim et al. as taught by Kato et al. because it is known in the art to improve reliability, reduces thermal cycling stress, and increase performance.
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the prior art teaches or suggests wherein each of the first length side and the second length side has a groove that is located at the first bonding portion of the lead and is recessed inward in the second direction in the plan view (in claim 3), or the first bonding portion of the lead includes a tapered portion, and a width in the second direction between the first length side and the second length side at a position in the tapered portion becomes smaller as the position in the tapered portion approaches the coupling portion (in claim 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893