Prosecution Insights
Last updated: April 19, 2026
Application No. 18/456,736

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Final Rejection §102
Filed
Aug 28, 2023
Examiner
TOBERGTE, NICHOLAS J
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Aaltosemi Inc.
OA Round
2 (Final)
94%
Grant Probability
Favorable
3-4
OA Rounds
1y 11m
To Grant
96%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
837 granted / 886 resolved
+26.5% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
28 currently pending
Career history
914
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
38.3%
-1.7% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
11.9%
-28.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 886 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 1/27/26 have been fully considered but they are not persuasive. Applicant argues that the encapsulating layer of Oh does not teach a first side and a second side opposite the first side with a conductive via in communication between the first side and the second side. This is not persuasive because the sides need not be planar as discussed in the rejection below. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al US 2019/0139853. Pertaining to claims 1 and 6, Oh teaches an electronic package, comprising: a circuit portion having at least one insulating layer and a circuit layer bonded to the insulating layer, wherein the insulating layer 141 is defined with a first surface and a second surface opposing the first surface, and the circuit layer 140 is exposed from the first surface of the insulating layer; an electronic element 120+125 disposed on the first surface of the insulating layer of the circuit portion and electrically connected to the circuit layer; an encapsulating layer 130 formed on the first surface of the insulating layer of the circuit portion and covering the electronic element, wherein the encapsulating layer is an Ajinomoto build-up film [0082] and is defined with a first side and a second side opposite to the first side; and a wiring layer formed on the encapsulating layer, wherein the wiring layer is formed with at least one conductive via in the encapsulating layer, and the at least one conductive via is electrically connected to the circuit layer, wherein the first side of the encapsulating layer is in communication with the second side of the encapsulating layer by the at least one conductive via. See Figure 16 marked up below and note that the encapsulating layers second side is the side opposite the first side regardless of what plane or topology is present as “side” does not imply a specific shape or structure. PNG media_image1.png 380 752 media_image1.png Greyscale PNG media_image2.png 368 600 media_image2.png Greyscale Pertaining to claims 2 and 7, Oh teaches the electronic package of claims 1 and 6, wherein the electronic element is a passive element. [0104] Oh teaches that alternatively to active elements, that 120 could be replaced with a passive component. Pertaining to claims 3 and 8, Oh teaches the electronic package of claims 1 and 6, wherein the electronic element is electrically connected to the circuit layer via a plurality of conductive bumps. See [0086] (note bumps are not shown in Figure but taught in this paragraph) Pertaining to claims 4 and 9, Oh teaches the electronic package of claims 1 and 6, wherein a material forming the encapsulating layer is different from a material forming the insulating layer. The encapsulating layer is ABF as indicated above, layer 141 is described as something else in paragraph [0095] Pertaining to claims 5 and 10, Oh teaches the electronic package of claims 1 and 6, further comprising another wiring layer formed on the second surface of the insulating layer, wherein the another wiring layer is formed with at least one conductive blind via in the insulating layer, and the at least one conductive blind via is electrically connected to the circuit layer. See Figure 16 marked up below. PNG media_image3.png 360 762 media_image3.png Greyscale Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Aug 28, 2023
Application Filed
Oct 27, 2025
Non-Final Rejection — §102
Jan 27, 2026
Response Filed
Mar 18, 2026
Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR PACKAGE AND METHOD
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Patent 12575435
SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURING THE SAME
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ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
94%
Grant Probability
96%
With Interview (+2.0%)
1y 11m
Median Time to Grant
Moderate
PTA Risk
Based on 886 resolved cases by this examiner. Grant probability derived from career allow rate.

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