DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/28/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 8-10, 12, 15, 16, 18, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al., US 2021/0202626.
Regarding claim 1, Jeon teaches (at least in Figures 3 and 4) an electronic device comprising: a display panel including a first region (A1) and a second region (A2) spaced apart from the first region, the first region including a transmissive region (TA) and an element region (PA), wherein the display panel includes: a base layer (sub); a circuit layer (PCL) disposed on the base layer, the circuit layer including a pixel circuit (PCL) and a barrier wall (TOL) disposed in the element region; an element layer disposed on the circuit layer (LDL), the element layer including a plurality of light emitting elements (LD) and a pixel defining film (PDL); and an encapsulation layer (OL) disposed on the element layer, the pixel defining film includes: a pixel defining pattern (PDL) disposed in the element region; and a pixel defining layer disposed in the second region (see Figure 3, pixel defining layer is in the element region for A1 and A2 to define the pixels), and a side surface of the pixel defining pattern is in contact with a side surface of the barrier wall (see Figure 4, side surface of PDL is in contact with side surface of TOL).
Regarding claim 2, Jeon teaches the invention as explained above regarding claim 1 and further teaches the circuit layer further includes a plurality of organic layers (INS2, PSV, [0080 and 0085]), the plurality of organic layers includes a first organic layer (INS2) disposed in the transmissive region and the element region, and the barrier wall is disposed on the first organic layer (see Figure 4, TOL disposed on INS2).
Regarding claim 8, Jeon teaches the invention as explained above regarding claim 1 and further teaches the barrier wall completely surrounds the pixel defining pattern in a plan view (see Figure 3, barrier wall which comprises all of TA, surrounds pixel defining patterns in PA area).
Regarding claim 9, Jeon teaches the invention as explained above regarding claim 1 and further teaches the barrier wall includes a plurality of barrier wall portions (see TA in Figure 3, plurality) spaced apart from each other (see Figure 3), and the plurality of barrier wall portions is arranged adjacent to the pixel defining pattern (pixel defining pattern in PA, see Figure 3).
Regarding claim 10, Jeon teaches the invention as explained above regarding claim 9 and further teaches the plurality of barrier wall portions includes a first barrier wall portion, a second barrier wall portion, a third barrier wall portion, and a fourth barrier wall portion (see Figure 3, four TA portions surrounding one PA portion), the first barrier wall portion and the third barrier wall portion face each other with the pixel defining pattern between the first barrier wall portion and the third barrier wall portion (see Figure 3), and the second barrier wall portion and the fourth barrier wall portion face each other with the pixel defining pattern between the second barrier wall portion and the fourth barrier wall portion (see Figure 3).
Regarding claim 12, Jeon teaches the invention as explained above regarding claim 9 and further teaches the plurality of barrier wall portions includes a first barrier wall portion, a second barrier wall portion, a third barrier wall portion, a fourth barrier wall portion (Figure 3, the TA regions that surround a single PA region), a fifth barrier wall portion, a sixth barrier wall portion, and a seventh barrier wall portion (Figure 3, upper TA regions that are on 3 sides of a separate PA region), the first and second barrier wall portions and the fifth and sixth barrier wall portions face each other with the pixel defining pattern between the first and second barrier wall portions and the fifth and sixth barrier wall portions (see Figure 3), and the third and fourth barrier wall portions and the seventh barrier wall portion face each other with the pixel defining pattern between the third and fourth barrier wall portions and the seventh barrier wall portion (see Figure 3).
Regarding claim 15, Jeon teaches the invention as explained above regarding claim 12 and further teaches the plurality of barrier wall portions further includes an eighth barrier wall portion, and the third and fourth barrier wall portions and the seventh and eighth barrier wall portions face each other with the pixel defining pattern between the third and fourth barrier wall portions and the seventh and eighth barrier wall portions (see Figure 3, pattern repeats multiple times more than shown, therefore an eighth barrier wall portion would also exist in the same pattern).
Regarding claim 16, Jeon teaches (at least in Figures 3 and 4) an electronic device comprising: a base layer (sub); a first organic layer disposed on the base layer (INS2, [0080]); a barrier wall (TOL) disposed on the first organic layer; a second organic layer (INS2, [0080-may be multiple layers]) disposed on the first organic layer; a third organic (PSV [0085]) layer disposed on the second organic layer; and a pixel defining pattern (PDL) disposed on the third organic layer and extending toward the barrier wall and making contact with the barrier wall (see Figure 4).
Regarding claim 18, Jeon teaches the invention as explained above regarding claim 16 and further teaches a height of the barrier wall is greater than a thickness of the second organic layer (second organic layer INS2 and barrier wall TOL, see Figure 4).
Regarding claim 19, Jeon teaches the invention as explained above regarding claim 16 and further teaches the barrier wall completely surrounds the pixel defining pattern in a plan view (see Figure 3).
Regarding claim 20, Jeon teaches the invention as explained above regarding claim 16 and further teaches the barrier wall includes a plurality of barrier wall portions spaced apart from each other (see Figure 3), and the plurality of barrier wall portions is arranged adjacent to the pixel defining pattern (see Figure 3).
Allowable Subject Matter
Claims 3-7, 11, 13, 14 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or suggest the plurality of organic layers further includes a second organic layer disposed on the first organic layer and a third organic layer disposed on the second organic layer and the barrier wall is in contact with the second organic layer but is spaced apart from the third organic layer. The prior art further fails to teach or suggest bridge barrier wall portions, or a length of the seventh barrier wall portion is longer than each of the lengths of the first to sixth barrier wall portions. Further, the prior art fails to teach or suggest the pixel defining pattern is in contact with an upper surface of the third organic layer, a side surface of the third organic layer, an upper surface of the second organic layer, and a side surface of the barrier wall, and the side surface of the third organic layer is spaced apart from the barrier wall.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Pang, US 2010/01339933 teaches a display comprising a circuit layer and pixel defining layer with barrier wall in the element region.
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MARY ELLEN BOWMAN
Examiner
Art Unit 2875
/MARY ELLEN BOWMAN/Primary Examiner, Art Unit 2875