DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 14 July 2026 has been entered.
Response to Amendment
The Office acknowledges receipt on 14 July 2026 of Applicants’ amendments in which claims 1, 2, and 10 are amended and claim 12 is newly added.
Response to Arguments
Applicants’ arguments filed 14 July 2026 have been fully considered but they are not persuasive.
Applicants’ argue, in the first paragraph of page 8 and with respect to claim 1 (and similarly with respect to independent claims 2 and 10), that:
Jones … only teaches the length relationship, LG2 > Lf, opposite to the claimed length relationship. Jones introduces the length LG2 only to compare it with the length LG2 at the bottom of the gate 32. See also [0077]. There is no specific teaching or suggestion about the claimed length relationship LG2 < Lf.
Claim 1 is rejected over the combined teachings of Jones, Saito, and Kondou and recites, in relevant part, “a length of the conductive layer in the second direction is greater than a length of the third electrode in the second direction.” Claims 2 and 10 are rejected over the same art and recite the same feature. Jones teaches in Fig. 1 and paragraphs [0056, 0085] a length (Lf) of the conductive layer (33) in the second direction (horizontal) is greater than a length (LG1) of the third electrode (32) in the second direction (horizontal). It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant. MPEP §2144(IV). As this principle applies to the present circumstance, Jones teaches the subject matter Applicants have identified for distinguishing the claim from the prior art. And with respect to the Office establishing a prima facie basis for rejecting the claim, Jones need not identify any motivation for having this subject matter because Jones is not being modified to include this subject matter. Additionally, because Jones need not identify a motivation for the recited subject matter, it follows from both this fact and the cited portion of the MPEP above that Jones need not teach that such subject matter achieves the same advantage or result discovered by Applicants.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jones et al. (US20210111254A1) in view of Saito et al. (US20180076311A1), and Kondou (US20120217581A1).
Regarding claim 1, Jones teaches in Fig. 1 a semiconductor device, comprising:
a first semiconductor layer (20) including a nitride semiconductor {[0052, 0053]};
a second semiconductor layer (22) located on the first semiconductor layer (20), the second semiconductor layer (22) including a nitride semiconductor {[0052, 0053]};
a first electrode (drain 30) located on the second semiconductor layer (22) {[0055]};
a second electrode (source 30) located on the second semiconductor layer (122) and arranged with the first electrode (drain 30) in a second direction (horizontal) crossing a first direction (vertical), the first direction (vertical) being from the first semiconductor layer (20) toward the second semiconductor layer (22) {[0055]};
a third electrode (32) positioned above the second semiconductor layer (22) with an insulating film part (26) interposed, the third electrode (32) being positioned between the first electrode (drain 30) and the second electrode (source 30) {[0055]};
an insulating region (27, 28) located on the second semiconductor layer (22), the insulating region (27, 28) being between the first electrode (drain 30) and the second electrode (source 30) and next to the first electrode (drain 30), the insulating region (27, 28) including a first insulating portion (27) and a second insulating portion (portion of 28), the second insulating portion (portion of 28) being positioned above the first insulating portion (27) {[0057, 0072}; and
a conductive layer (33) located between the first insulating portion (27) and the second insulating portion (portion of 28) {[0057]},
wherein a length (Lf) of the conductive layer (33) in the second direction (horizontal) is greater than a length (LG1) of the third electrode (32) in the second direction (horizontal) {Fig. 1; [0056, 0085]}.
Jones does not teach an entire bottom surface of the third electrode being in contact with the insulating film.
In an analogous art, Saito teaches in Fig. 1 and paragraph [0036] an entire bottom surface of a third electrode (22) being in contact with an insulating film (20). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device based on the teachings of Saito – such that an entire bottom surface of the third electrode being in contact with the insulating film – to suppress[] a gate leak current of the HEMT. Saito [0036].
Jones as modified by Saito does not teach the conductive layer being electrically connected with the first electrode.
In an analogous art, Kondou teaches in Figs. 1-3B and paragraph [0039] a conductive layer (FP15) being electrically connected with a first electrode (electrode above 50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device as modified by Saito based on the teachings of Kondou – such that the conductive layer is electrically connected with the first electrode – to: (1) create a channel more reliably {Kondou [0066]}, (2) decreas[e] the on resistance {Kondou [0056]}, and/or (3) alleviate the electrical field concentration in the drain-side end portion of the gate electrode {Kondou [0056]}. Moreover, all the claimed elements (e.g., conductive layer, electrode) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kondou) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 2, Jones teaches in Fig. 1 a semiconductor device, comprising:
a first semiconductor layer (20) including a nitride semiconductor {[0052, 0053]};
a second semiconductor layer (22) located on the first semiconductor layer (20), the second semiconductor layer (22) including a nitride semiconductor {[0052, 0053]};
a first electrode (source 30) located on the second semiconductor layer (22) {[0055]};
a second electrode (drain 30) located on the second semiconductor layer (22), the second electrode (drain 30) being arranged with the first electrode (source 30) in a second direction (horizontal) crossing a first direction (vertical), the first direction (vertical) being from the first semiconductor layer (20) toward the second semiconductor layer (22) {[0055]};
a third electrode (32) positioned above the second semiconductor layer (22) with an insulating film part (26) interposed, the third electrode (32) being positioned between the first electrode (source 30) and the second electrode (drain 30) in the second direction (horizontal) {[0055]};
an insulating region (27, 28) located on the second semiconductor layer (22), the insulating region (27, 28) being between the first electrode (source 30) and the second electrode (drain 30) and next to the first electrode (source 30), the insulating region (27, 28) including a first insulating portion (27) and a second insulating portion (28), the second insulating portion (28) being positioned above the first insulating portion (27) {[0057, 0072}; and
a conductive layer (33) located between the first insulating portion (27) and the second insulating portion (28) {[0057]},
wherein a length (Lf) of the conductive layer (33) in the second direction (horizontal) is greater than a length (LG1) of the third electrode (32) in the second direction (horizontal) {Fig. 1; [0056, 0085]}.
Jones does not teach an entire bottom surface of the third electrode being in contact with the insulating film.
Saito teaches in Fig. 1 and paragraph [0036] an entire bottom surface of a third electrode (22) being in contact with an insulating film (20). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device based on the teachings of Saito – such that an entire bottom surface of the third electrode being in contact with the insulating film – to suppress[] a gate leak current of the HEMT. Saito [0036].
Jones as modified by Saito does not teach the conductive layer being connected to a circuit, the conductive layer being set to a lower potential than the second electrode by the circuit.
Kondou teaches in Figs. 1-3B and paragraph [0039] a conductive layer (FP15) being connected to a circuit (e.g., voltages sources, resistive load, 90) {Fig. 3A/3B}, the conductive layer (FP15) being set to a lower potential than the second electrode (electrode above 50) by the circuit (e.g., voltages sources, resistive load, 90). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device as modified by Saito based on the teachings of Kondou – such that the conductive layer is connected to a circuit, the conductive layer being set to a lower potential than the second electrode by the circuit – to: (1) create a channel more reliably {Kondou [0066]}, (2) decreas[e] the on resistance {Kondou [0056]}, and/or (3) alleviate the electrical field concentration in the drain-side end portion of the gate electrode {Kondou [0056]}. Moreover, all the claimed elements (e.g., conductive layer, electrode) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kondou) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 3, Jones as modified by Saito and Kondou teaches the device according to claim 2, but Jones does not teach wherein the circuit includes a Zener diode.
Kondou teaches in Figs. 1-3B and paragraphs [0032, 0039] a circuit (e.g., voltages sources, resistive load, 90) includes a Zener diode (90). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device as modified by Saito and Kondou based on the further teachings of Kondou – such that the circuit includes a Zener diode – to: (1) create a channel more reliably {Kondou [0066]}, (2) decreas[e] the on resistance {Kondou [0056]}, and/or (3) alleviate the electrical field concentration in the drain-side end portion of the gate electrode {Kondou [0056]}. Moreover, all the claimed elements (e.g., circuit includes, Zener diode) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kondou) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 4, Jones as modified by Saito and Kondou teaches the device according to claim 1, and Jones further teaches further comprising:
a third insulating portion (portion of 28 directly between 33b and drain 30) located between the conductive layer (33) and the first electrode (drain 30), the third insulating portion (portion of 28 directly between 33b and drain 30) being arranged with the conductive layer (33) in a direction (horizontal) perpendicular to the first direction (vertical) {[0057]}.
Regarding claim 5, Jones as modified by Saito and Kondou teaches the device according to claim 1, and Jones further teaches wherein
the conductive layer (33) includes an end portion at the third electrode side (32).
Jones does not teach a distance along the second direction between the end portion and the first electrode is less than a distance along the second direction between the end portion and the third electrode.
Kondou teaches in Fig. 1 and paragraphs [0032, 0034] a distance along a second direction (horizontal) between an end portion (left-end portion) of a conductive layer (FP15) and a first electrode (electrode above 50) is less than a distance along the second direction (horizontal) between the end portion (left-end portion) and a third electrode (60b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device as modified by Saito and Kondou based on the further teachings of Kondou – such that a distance along the second direction between the end portion and the first electrode is less than a distance along the second direction between the end portion and the third electrode – so a plurality of field plates are separated from each other and arranged in the direction from the second semiconductor region … toward the drain region {Kondou [0027]} to thereby: (1) create a channel more reliably {Kondou [0066]}, (2) decreas[e] the on resistance {Kondou [0056]}, and/or (3) alleviate the electrical field concentration in the drain-side end portion of the gate electrode {Kondou [0056]}. Moreover, all the claimed elements (e.g., end portions, electrodes) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kondou) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 6, Jones as modified by Saito and Kondou teaches the device according to claim 1, but Jones does not teach further comprising:
a conductive member electrically connected with the third electrode,
the conductive member covering the third electrode,
the conductive layer being arranged with the conductive member in the second direction.
Kondou teaches in Fig. 1 and paragraph [0024]:
a conductive member (via disposed directly on 60) electrically connected with a third electrode (60),
the conductive member (via disposed directly on 60) covering the third electrode (60),
a conductive layer (FP15) being arranged with the conductive member (via disposed directly on 60) in a second direction (horizontal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device as modified by Saito and Kondou based on the further teachings of Kondou, as identified above, to: (1) create a channel more reliably {Kondou [0066]}, (2) decreas[e] the on resistance {Kondou [0056]}, and/or (3) alleviate the electrical field concentration in the drain-side end portion of the gate electrode {Kondou [0056]}. Moreover, all the claimed elements (e.g., conductive member, electrode, conductive layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kondou) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 7, Jones as modified by Saito and Kondou teaches the device according to claim 1, but Jones does not teach wherein the first electrode includes:
a first electrode part; and
a first extension part extending from an upper end portion of the first electrode part toward the second electrode side, and
at least a portion of the conductive layer is positioned between the first extension part and the second semiconductor layer.
Kondou teaches in Fig. 1 a first electrode part; and a first extension part extending from an upper end portion of the first electrode part toward a second electrode side (electrode connected to 41), and at least a portion of a conductive layer (FP15) is positioned between the first extension part and a second semiconductor layer (20) {see Annotated Copy of Kondou’s Fig. 1, below}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device as modified by Saito and Kondou based on the further teachings of Kondou, as identified in the preceding sentence, to: (1) create a channel more reliably {Kondou [0066]}, (2) decreas[e] the on resistance {Kondou [0056]}, and/or (3) alleviate the electrical field concentration in the drain-side end portion of the gate electrode {Kondou [0056]}. Moreover, all the claimed elements (e.g., first electrode part, first extension part, electrode, conductive layer, semiconductor layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kondou) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
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Regarding claim 8, Jones as modified by Saito and Kondou teaches the device according to claim 7, but Jones does not teach wherein a length along the second direction of the conductive layer is greater than a length along the second direction of the first extension part.
Kondou teaches in Fig. 1 a length along a second direction (horizontal) of a conductive layer (FP15) is greater than a length along the second direction (horizontal) of a first extension part {see the Annotated Copy of Kondou’s Fig. 1, provided with respect to intermediate claim 7}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device as modified by Saito and Kondou based on the further teachings of Kondou – such that a length along the second direction of the conductive layer is greater than a length along the second direction of the first extension part – to: (1) create a channel more reliably {Kondou [0066]}, (2) decreas[e] the on resistance {Kondou [0056]}, and/or (3) alleviate the electrical field concentration in the drain-side end portion of the gate electrode {Kondou [0056]}. Moreover, all the claimed elements (e.g., conductive layer, extension part) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kondou) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 9, Jones as modified by Saito and Kondou teaches a semiconductor module, comprising:
the device (modified 100) according to claim 2.
Jones does not teach:
the circuit,
the device including
a contact part contacting the conductive layer, and
an electrode pad electrically connected with the contact part,
the circuit being electrically connected with the electrode pad,
the first electrode or the second electrode being electrically connected to an external load.
Kondou teaches in Figs. 1-3B:
a circuit (e.g., voltages sources, resistive load, 90) {Figs. 3A, 3B},
a device (e.g., 1, excluding 90) including
a contact part (e.g., wire connecting FP15 and 92) contacting a conductive layer (FP15), and
an electrode pad (node interconnecting wire and 90) electrically connected with the contact part (e.g., wire connecting FP15 and 92),
the circuit (e.g., voltages sources, resistive load, 90) being electrically connected with the electrode pad (node interconnecting wire and 90),
a first electrode (electrode connected to 41) or a second electrode (electrode connected to 51) being electrically connected to an external load (resistive load in Figs. 3A, 3B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device as modified by Saito and Kondou based on the further teachings of Kondou, as identified above, to: (1) create a channel more reliably {Kondou [0066]}, (2) decreas[e] the on resistance {Kondou [0056]}, and/or (3) alleviate the electrical field concentration in the drain-side end portion of the gate electrode {Kondou [0056]}. Moreover, all the claimed elements (e.g., as identified above) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kondou) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Examiner’s Note: the recitation of “the first electrode or the second electrode being electrically connected to an external load” is directed to a manner in which the claimed subject matter is intended to be employed because the external load is not a constituent component of the recited device. Accordingly, this subject matter does not further structurally limit the claimed invention or contribute to distinguishing it from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding claim 10, Jones teaches in Fig. 1 a semiconductor device, comprising:
a first semiconductor layer (20) including a nitride semiconductor {[0052, 0053]};
a second semiconductor layer (22) located on the first semiconductor layer (20), the second semiconductor layer (22) including a nitride semiconductor {[0052, 0053]};
a first electrode (drain 30) located on the second semiconductor layer (22) {[0055]};
a second electrode (source 30) located on the second semiconductor layer (122) and arranged with the first electrode (drain 30) in a second direction (horizontal) crossing a first direction (vertical), the first direction (vertical) being from the first semiconductor layer (20) toward the second semiconductor layer (22) {[0055]};
a third electrode (32) positioned above the second semiconductor layer (22) with an insulating film part (26) interposed, the third electrode (32) being positioned between the first electrode (drain 30) and the second electrode (source 30) {[0055]};
an insulating region (27, 28) located on the second semiconductor layer (22), the insulating region (27, 28) being between the first electrode (drain 30) and the second electrode (source 30) and next to the first electrode (drain 30), the insulating region (27, 28) including a first insulating portion (27) and a second insulating portion (portion of 28), the second insulating portion (portion of 28) being positioned above the first insulating portion (27) {[0057, 0072}; and
a conductive layer (33) located between the first insulating portion (27) and the second insulating portion (portion of 28) {[0057]},
wherein a length (Lf) of the conductive layer (33) in the second direction (horizontal) is greater than a length (LG1) of the third electrode (32) in the second direction (horizontal) {Fig. 1; [0056, 0085]}.
Jones does not teach a distance between the third electrode and the second semiconductor layer being greater than a distance between the first electrode and the second semiconductor layer.
Saito teaches in Fig. 1 a distance between the third electrode (22) and a second semiconductor layer (16) being greater than a distance between a first electrode (28) and the second semiconductor layer (16). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device based on the teachings of Saito – such that a distance between the third electrode and the second semiconductor layer being greater than a distance between the first electrode and the second semiconductor layer – so an ohmic contact is may be formed and/or the first electrode is electrically connected to the channel layer … via the barrier layer (i.e., the second semiconductor layer). Saito [0041].
Jones as modified by Saito does not teach the conductive layer being electrically connected with the first electrode.
Kondou teaches in Figs. 1-3B and paragraph [0039] a conductive layer (FP15) being electrically connected with a first electrode (electrode above 50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device as modified by Saito based on the teachings of Kondou – such that the conductive layer is electrically connected with the first electrode – to: (1) create a channel more reliably {Kondou [0066]}, (2) decreas[e] the on resistance {Kondou [0056]}, and/or (3) alleviate the electrical field concentration in the drain-side end portion of the gate electrode {Kondou [0056]}. Moreover, all the claimed elements (e.g., conductive layer, electrode) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kondou) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 11, Jones as modified by Saito and Kondou teaches the device according to claim 1, but Jones does not teach wherein the third electrode is entirely located between the second semiconductor layer and the conductive layer.
Saito teaches in Fig. 1 and paragraph [0075] a third electrode (22) is entirely located between a second semiconductor layer (16) and a conductive layer (30). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device as modified by Saito and Kondou based on the further teachings of Saito – such that the third electrode is entirely located between the second semiconductor layer and the conductive layer – so: (1) current collapse can be effectively suppressed {Saito [0075]}, (2) the conductive layer may more readily be electrically connected to the source electrode {Saito [0050]}, and/or (3) manufacturing resources (e.g., materials, manufacturing operations, etc.) may be reduced {Saito [0040, 0052]}. Moreover, all the claimed elements (e.g., electrode, semiconductor layer, conductive layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Saito) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Saito, and Kondou and as applied to claim 1 above, and further in view of Hao et al. (US20220393024A1).
Regarding claim 12, Jones as modified by Saito and Kondou teaches the device according to claim 1, but Jones does not teach wherein the conductive layer is located at a layer level above a layer level of the third electrode.
In an analogous art, Hao teaches in Fig. 1 and paragraph [0045] a conductive layer (130) is located at a layer level above a layer level of a third electrode (118). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jones’ semiconductor device as modified by Saito and Kondou based on the teachings of Hao, to achieve the above-identified subject matter, to reduce the peak electric field at the gate edge, improv[e] uniformity of electric field distribution[,] … increas[e] breakdown voltage[, and/or] reshape the electrical field between the gate electrode … and the drain electrode. Moreover, all the claimed elements (e.g., conductive layer, electrode) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hao) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Takahashi (US20080203496A1) teaches a gate electrode 20 and first field plates 22 a to 22 d and 23 are provided on a field oxide film 19. The gate electrode 20 and first field plates 22 a to 22 d and 23 are covered with an insulating film 24. A high-voltage wiring conductor 28 is provided on the insulating film 24. A shielding electrode 29 is provided between the first field plate 22 a positioned closest to a source side and the high-voltage wiring conductor 28.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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