DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 11/25/2025 is acknowledged.
Claims 9-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/25/2025.
New claims 21-25 are acknowledged and examined as being drawn to elected Group I.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-8, 21 and 23-25 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Monadgemi (US-20240312919-A1).
Regarding claim 1, Monadgemi teaches a computing component (Fig.5C 590; ¶0049), comprising:
a printed circuit board (PCB) (Fig.5C 593; ¶0049); and
an unsingulated semiconductor package (Fig.5C 500; ¶0049) electrically coupled to the PCB (593), the unsingulated semiconductor package (500) comprising:
a plurality of integrated circuits (Fig.5C 515 and 517; ¶0050) provided on an unsingulated substrate segment (Fig.5C 510; ¶0050), the unsingulated substrate segment (510) comprising:
a first substrate segment (Fig.5C 501A; ¶0050);
a second substrate segment (Fig.5C 501B; ¶0050) adjacent the first substrate segment (501A); and
an unsingulated area (Fig.5C 535; ¶0050) provided between the first substrate segment (501A) and the second substrate segment (501B).
Regarding claim 2, Monadgemi teaches the computing component of claim 1, wherein the unsingulated substrate segment (510) is associated with a plurality of saw streets (535 is a saw street; ¶0050).
Regarding claim 4, Monadgemi teaches the computing component of claim 1, wherein:
a first integrated circuit (517 left) of the plurality of integrated circuits (515 and 517) is provided on the first substrate segment (501A);
a second integrated circuit (517 right) of the plurality of integrated circuits (515 and 517) is provided on the second substrate segment (501B); and
a third integrated circuit (Fig.2B 220C) of the plurality of integrated circuits (515 and 517) is provided on the unsingulated area (535).
Regarding claim 5, Monadgemi teaches the computing component of claim 1, wherein the unsingulated area (535) is associated with a saw street that was skipped during a semiconductor package singulation process (see Fig.6).
Regarding claim 6, Monadgemi teaches the computing component of claim 1, wherein each of the plurality of integrated circuits (515 and 517) include one or more semiconductor dies (¶0021).
Regarding claim 7, Monadgemi teaches the computing component of claim 1, wherein the plurality of integrated circuits (515 and 517) are encapsulated by a single cover (Fig.5C 542; ¶0046).
Regarding claim 8, Monadgemi teaches the computing component of claim 1, wherein the unsingulated semiconductor package (500) is separated from a plurality of other unsingulated semiconductor packages (500) during a semiconductor package singulation process (see Fig.6).
Regarding claim 21, Monadgemi teaches an unsingulated semiconductor package (Fig.5C 500; ¶0049), comprising:
an unsingulated substrate segment (Fig.5C 510; ¶0050) comprising a first portion (Fig.5C 501A; ¶0050), a second portion (Fig.5C 501B; ¶0050) and a saw street (Fig.5C 535; ¶0050) provided between the first portion (501A) and the second portion (501B);
a first integrated circuit (Fig.5C 517; ¶0050) coupled to the substrate segment (510) such that at least a portion of the first integrated circuit (517) is on the first portion (501A); and
a second integrated circuit (Fig.5C 515; ¶0050) coupled to the substrate segment (510) such that at least a portion of the second integrated circuit (515) is provided on the saw street (535).
Regarding claim 23, Monadgemi teaches the unsingulated semiconductor package of claim 21, further comprising a plurality of connection mechanisms (Fig.5C 541; ¶0047) provided on a surface of the unsingulated substrate segment (510).
Regarding claim 24, Monadgemi teaches the unsingulated semiconductor package of claim 21, further comprising a molding compound (Fig.5C 542; ¶0046) that encapsulates the first integrated circuit (517) and the second integrated circuit (515).
Rergarding claim 25, Monadgemi teaches the unsingulated semiconductor package of claim 21, wherein the saw street (535) that is provided between the first portion (501A) and the second portion (501B) was skipped during a substrate singulation process (see Fig.6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Monadgemi.
Regarding claim 3, Monadgemi teaches the computing component of claim 2.
Monadgemi does not teach wherein each of the plurality of saw streets have a width between 0.25 millimeters (mm) and 1.3 mm.
However, it would have been obvious to form the saw street within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Claim(s) 14-20 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Monadgemi in view of Paek (US-20240274578-A1).
Regarding claim 14, Monadgemi teaches a device (Fig.5C 500; ¶0049), comprising:
a substrate (Fig.5C 510; ¶0050) having at least one saw street (Fig.5C 535; ¶0050) that separates the substrate into first (Fig.5C 501A; ¶0050) and second (Fig.5C 501B; ¶0050) adjacent sections;
a plurality of dies (Fig.5C 515 and 517; ¶0050) provided on a first surface (top surface) of the substrate (510), wherein the plurality of memory dies (515 and 517) includes a first memory die (517 left) mounted on the first section (501A), a second memory die (517 right) mounted on the second section (501B), and a third memory die (515) mounted in an area between the first (501A) and second (501B) sections and spanning the at least one saw street (535);
means for electrically connecting (Fig.5C 512; ¶0046) the plurality of dies (515 and 517) to the substrate (510);
means for encapsulating (Fig.5C 542; ¶0046) the plurality of dies (515 and 517); and
external electrical connection means (Fig.5C 541; ¶0047) attached to a second surface (bottom surface) of the substrate (510) opposing the first surface (top surface) of the substrate (510), the external electrical connection means (541) allowing the device to be connected to host device (Fig.5C 593; ¶0049).
Monadgemi does not explicitly teach wherein the device is a memory device and the dies are memory dies.
Paek teaches a device comprising NAND memory dies (Fig.1 104; ¶0012 of Paek) thyat are electrically connected to a substrate (Fig.1 106; ¶0012 of Paek) with wires (Fig.1 128; ¶0013 of Paek).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the dies (515 and 517 of Monadgemi) to be memory dies (104 of Paek) and for the dies to be connected via wires (128 of Paek) instead of solder balls (512 of Monadgemi) to arrive at the claimed invention. These differences are obvious because they are well-known alternatives to the components taught by Monadgemi and are simply a matter of design choice.
Regarding claim 15, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14, wherein the electrically connecting means comprise bond wires (126 of Paek can easily substitute 512 of Monadgemi).
Regarding claim 16, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14.
The aforementioned combination does not teach wherein the at least one saw street has a width between 0.25 millimeters (mm) and 1.3 mm.
However, it would have been obvious to form the saw street within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 17, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14, wherein the memory dies comprise NAND dies (¶0012 of Paek).
Regarding claim 18, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14, wherein the at least one saw street (535 of Monadgemi) is a saw street that was skipped during a semiconductor package singulation process (see Fig.6 of Monadgemi).
Regarding claim 19, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14, wherein the encapsulating means comprises a mold compound (¶0046 of Monadgemi).
Regarding claim 20, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14, wherein the external electrical connection means comprises solder balls (¶0047 of Monadgemi).
Regarding claim 22, Monadgemi teaches the unsingulated semiconductor package of claim 21.
Monadgemi does not teach wherein at least one of the first integrated circuit and the second integrated circuit is a memory die.
Paek teaches a device comprising NAND memory dies (Fig.1 104; ¶0012 of Paek) thyat are electrically connected to a substrate (Fig.1 106; ¶0012 of Paek) with wires (Fig.1 128; ¶0013 of Paek).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the dies (515 and 517 of Monadgemi) to be memory dies (104 of Paek) and for the dies to be connected via wires (128 of Paek) instead of solder balls (512 of Monadgemi) to arrive at the claimed invention. These differences are obvious because they are well-known alternatives to the components taught by Monadgemi and are simply a matter of design choice.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (US-20250157922-A1 and US-20240112971-A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/T.J.K./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817