DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 05/26/2026, with respect to the rejection(s) of claim(s) 1-2, 4-8, 21 and 23-25 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of secondary reference Paek.
Applicant's arguments filed 05/26/2026 with respect to the rejection(s) of claim(s) 14-20 and 22 have been fully considered but they are not persuasive. While it is true that Paek does not disclose a saw street or unsingulated area, Paek is not relied upon to teach or modify these features. Primary reference Monadgemi teaches these features and only requires modification for different features, such as the integrated circuit dies. Accordingly, the rejection of record under 35 U.S.C. 103 is upheld.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-3, 5, 7-8, 14-21 and 23-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Monadgemi (US-20240312919-A1) in view of Paek (US-20240274578-A1).
Regarding claim 1, Monadgemi teaches a computing component (Fig.5C 590; ¶0049), comprising:
a printed circuit board (PCB) (Fig.5C 593; ¶0049); and
an unsingulated semiconductor package (Fig.5C 500; ¶0049) electrically coupled to the PCB (593), the unsingulated semiconductor package (500) comprising:
a plurality of integrated circuits (Fig.5C 515 and 517; ¶0050) provided on an unsingulated substrate segment (Fig.5C 510; ¶0050), the unsingulated substrate segment (510) comprising:
a first integrated circuit (517 left) of the plurality of integrated circuits (515 and 517) provided on a first substrate segment (Fig.5C 501A; ¶0050);
a second substrate segment (Fig.5C 501B; ¶0050) adjacent the first substrate segment (501A);
a second integrated circuit (517 right) of the plurality of integrated circuits (515 and 517) provided on the second substrate segment (501B);
an unsingulated area (Fig.5C 535; ¶0050) provided between the first substrate segment (501A) and the second substrate segment (501B);
a third integrated circuit (515) of the plurality of integrated circuits (515 and 517) provided on the unsingulated area (535).
Monadgemi does not teach wherein the plurality of integrated circuits are memory dies;
a first plurality of bond wires electrically coupling the first memory die to the first substrate segment;
a second plurality of bond wires electrically coupling the second integrated circuit to the second substrate segment; and
a third plurality of bond wires electrically coupling the third integrated circuit to the unsingulated area.
Paek teaches a device comprising NAND memory dies (Fig.1 104; ¶0012 of Paek) that are electrically connected to a substrate (Fig.1 106; ¶0012 of Paek) with wires (Fig.1 128; ¶0013 of Paek).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the dies (515 and 517 of Monadgemi) to be memory dies (104 of Paek) and for the dies to be connected via wires (128 of Paek) instead of solder balls (512 of Monadgemi) to arrive at the claimed invention. These differences are obvious because they are well-known alternatives to the components taught by Monadgemi and are simply a matter of design choice.
Regarding claim 2, the aforementioned combination of Monadgemi in view of Paek from claim 1 teaches the computing component of claim 1, wherein the unsingulated substrate segment (510 of Monadgemi) is associated with a plurality of saw streets (535 is a saw street; ¶0050 of Monadgemi).
Regarding claim 3, the aforementioned combination of Monadgemi in view of Paek from claim 2 teaches the computing component of claim 2.
The aforementioned combination does not teach wherein each of the plurality of saw streets have a width between 0.25 millimeters (mm) and 1.3 mm.
However, it would have been obvious to form the saw street within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 5, the aforementioned combination of Monadgemi in view of Paek from claim 1 teaches the computing component of claim 1, wherein the unsingulated area (535 of Monadgemi) is associated with a saw street that was skipped during a semiconductor package singulation process (see Fig.6 of Monadgemi).
Regarding claim 7, the aforementioned combination of Monadgemi in view of Paek from claim 1 teaches the computing component of claim 1, wherein the plurality of memory dies (515 and 517 of Monadgemi) are encapsulated by a single cover (Fig.5C 542; ¶0046 of Monadgemi).
Regarding claim 8, the aforementioned combination of Monadgemi in view of Paek from claim 1 teaches the computing component of claim 1, wherein the unsingulated semiconductor package (500 of Monadgemi) is separated from a plurality of other unsingulated semiconductor packages (500 of Monadgemi) during a semiconductor package singulation process (see Fig.6 of Monadgemi).
Regarding claim 14, Monadgemi teaches a device (Fig.5C 500; ¶0049), comprising:
a substrate (Fig.5C 510; ¶0050) having at least one saw street (Fig.5C 535; ¶0050) that separates the substrate into first (Fig.5C 501A; ¶0050) and second (Fig.5C 501B; ¶0050) adjacent sections;
a plurality of dies (Fig.5C 515 and 517; ¶0050) provided on a first surface (top surface) of the substrate (510), wherein the plurality of memory dies (515 and 517) includes a first memory die (517 left) mounted on the first section (501A), a second memory die (517 right) mounted on the second section (501B), and a third memory die (515) attached to and mounted in an area between the first (501A) and second (501B) sections and spanning the at least one saw street (535);
means for electrically connecting (Fig.5C 512; ¶0046) the plurality of dies (515 and 517) to the substrate (510);
means for encapsulating (Fig.5C 542; ¶0046) the plurality of dies (515 and 517); and
external electrical connection means (Fig.5C 541; ¶0047) attached to a second surface (bottom surface) of the substrate (510) opposing the first surface (top surface) of the substrate (510), the external electrical connection means (541) allowing the device to be connected to host device (Fig.5C 593; ¶0049).
Monadgemi does not explicitly teach wherein the device is a memory device and the dies are memory dies.
Paek teaches a device comprising NAND memory dies (Fig.1 104; ¶0012 of Paek) that are electrically connected to a substrate (Fig.1 106; ¶0012 of Paek) with wires (Fig.1 128; ¶0013 of Paek).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the dies (515 and 517 of Monadgemi) to be memory dies (104 of Paek) and for the dies to be connected via wires (128 of Paek) instead of solder balls (512 of Monadgemi) to arrive at the claimed invention. These differences are obvious because they are well-known alternatives to the components taught by Monadgemi and are simply a matter of design choice.
Regarding claim 15, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14, wherein the electrically connecting means comprise bond wires (126 of Paek can easily substitute 512 of Monadgemi).
Regarding claim 16, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14.
The aforementioned combination does not teach wherein the at least one saw street has a width between 0.25 millimeters (mm) and 1.3 mm.
However, it would have been obvious to form the saw street within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 17, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14, wherein the memory dies comprise NAND dies (¶0012 of Paek).
Regarding claim 18, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14, wherein the at least one saw street (535 of Monadgemi) is a saw street that was skipped during a semiconductor package singulation process (see Fig.6 of Monadgemi).
Regarding claim 19, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14, wherein the encapsulating means comprises a mold compound (¶0046 of Monadgemi).
Regarding claim 20, the aforementioned combination of Monadgemi in view of Paek from claim 14 teaches the memory device of claim 14, wherein the external electrical connection means comprises solder balls (¶0047 of Monadgemi).
Regarding claim 21, Monadgemi teaches an unsingulated semiconductor package (Fig.5C 500; ¶0049), comprising:
an unsingulated substrate segment (Fig.5C 510; ¶0050) comprising a first portion (Fig.5C 501A; ¶0050), a second portion (Fig.5C 501B; ¶0050) and a saw street (Fig.5C 535; ¶0050) provided between the first portion (501A) and the second portion (501B);
a first integrated circuit (Fig.5C 517; ¶0050) coupled to the substrate segment (510) such that at least a portion of the first integrated circuit (517) is on the first portion (501A); and
a second integrated circuit (Fig.5C 515; ¶0050) attached to the unsingulated substrate segment (510) such that at least a portion of the second integrated circuit (515) is provided on the saw street (535).
Monadgemi does not teach wherein the plurality of integrated circuits are memory dies;
wherein the first memory die is coupled with a first plurality of bond wires; and
wherein the second memory die is attached with a second plurality of bond wires.
Paek teaches a device comprising NAND memory dies (Fig.1 104; ¶0012 of Paek) that are electrically connected to a substrate (Fig.1 106; ¶0012 of Paek) with wires (Fig.1 128; ¶0013 of Paek).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the dies (515 and 517 of Monadgemi) to be memory dies (104 of Paek) and for the dies to be connected via wires (128 of Paek) instead of solder balls (512 of Monadgemi) to arrive at the claimed invention. These differences are obvious because they are well-known alternatives to the components taught by Monadgemi and are simply a matter of design choice.
Regarding claim 23, the aforementioned combination of Monadgemi in view of Paek from claim 21 teaches the unsingulated semiconductor package of claim 21, further comprising a plurality of connection mechanisms (Fig.5C 541; ¶0047 of Monadgemi) provided on a surface of the unsingulated substrate segment (510 of Monadgemi).
Regarding claim 24, the aforementioned combination of Monadgemi in view of Paek from claim 21 teaches the unsingulated semiconductor package of claim 21, further comprising a molding compound (Fig.5C 542; ¶0046 of Monadgemi) that encapsulates the first memory die (517 of Monadgemi) and the second memory die (515 of Monadgemi).
Regarding claim 25, the aforementioned combination of Monadgemi in view of Paek from claim 21 teaches the unsingulated semiconductor package of claim 21, wherein the saw street (535 of Monadgemi) that is provided between the first portion (501A of Monadgemi) and the second portion (501B of Monadgemi) was skipped during a substrate singulation process (see Fig.6 of Monadgemi).
Regarding claim 26, the aforementioned combination of Monadgemi in view of Paek from claim 1 teaches the computing component of claim 1, wherein the unsingulated area (535 of Monadgemi) includes at least a portion of the first substrate segment (501A of Monadgemi) and at least a portion of the second substrate segment (501B of Monadgemi).
Regarding claim 27, the aforementioned combination of Monadgemi in view of Paek from claim 1 teaches the computing component of claim 1, wherein at least one of the plurality of memory dies (515 and 517 of Monadgemi) comprises a stack of memory dies (memory die stacks are well-known in the art and are not patentably distinct over a single memory die).
Regarding claim 28, the aforementioned combination of Monadgemi in view of Paek from claim 21 teaches the unsingulated semiconductor package of claim 21.
The aforementioned combination does not teach wherein the saw street has a width between 0.25 millimeters (mm) and 1.3 mm.
However, it would have been obvious to form the saw street within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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