DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Amendment of the title sent on 04/02/2026 has been accepted.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 has been amended with new claim language like “contacting an uppermost surface of the substrate”, though applicant argued that support for amendment can be found in Fig. 1, however the examiner couldn’t find the claim language “contacting an uppermost surface of the substrate” in the specification. Also Fig. 2 shows that first channel 120 contacting the uppermost surface of the active pattern 105, not the substrate 100, while active pattern 105 formed on the substrate 100. Accordingly, the amended claim language of “contacting an uppermost surface of the substrate” is a new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 has been amended with new claim language like “contacting an uppermost surface of the substrate”, though applicant argued that support for amendment can be found in Fig. 1, however the examiner couldn’t find the claim language “contacting an uppermost surface of the substrate” in the specification. Also Fig. 2 shows that first channel 120 contacting the uppermost surface of the active pattern 105, not the substrate 100, while active pattern 105 formed on the substrate 100. Accordingly, the scope of the amended claim language of “contacting an uppermost surface of the substrate” is unclear in describing and defining the claimed invention.
Claim 1, line 4 recited “an uppermost surface of the substrate” and line 7 recited “an upper surface of the substrate”, therefore the boundaries of the claims are not reasonably clear and also language in the claims is ambiguous, vague, incoherent, opaque, or otherwise unclear in describing and defining the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak, US 20040108558, in view of Ohno, US 20230012834.
Regarding claims 1 and 2, Kwak discloses a method of manufacturing a semiconductor device, the method comprising: performing a first selective epitaxial growth (SEG) process on a substrate to form a first channel (Fig.2a and [0018, 0037]; epitaxial layer 15 corresponds to a source/drain junction layer formed on the substrate 11,13 and at least a portion of the gate insulating film 29 overlap with the second epitaxial layer 15; because a portion of layer 15 is underneath the gate 31 and gate insulating layer 29, layer 15 could be referred to as a channel) contacting an uppermost surface of the substrate (examiner interpret contacting as “thermally contacting”, Fig.2a ; epitaxial layer 15 thermally contacting uppermost surface of the substrate 11,13 ) ; performing a first etching process to form a first recess (Fig.2b and [0024]; region 22 is formed by etching through the upper portion semiconductor substrate 11,13 and epitaxial layer 15) through the first channel and a first upper portion of the substrate, a sidewall of the first channel exposed (Fig.2b and [0024]; region 22 exposing the sidewall of epitaxial layer 15) by the first recess; performing a second SEG process to form a second channel (Fig.2f and [0031,0034]; channel region is formed as epitaxial layer 27 is grown on the semiconductor substrate 11, 13 and on the exposed sidewall of the epitaxial layer 15) on a surface of the substrate and the sidewall of the first channel exposed by the first recess; forming a gate structure (Fig.2f and [0037]; gate electrode 31); and forming an impurity region (Fig.2f and [0022, 0037]; epitaxial layer 15 is subjected to an implant process with other conventional impurities may be used) at a second upper portion of the substrate adjacent to the gate structure. Kwak substantially discloses the claimed invention of relates to method for manufacturing transistor including a sidewall of the first channel exposed by the first recess and forming a gate structure but is silent about the exposed sidewall being slanted with respect to an upper surface of the substrate and the gate structure is formed to fill the first recess in claim 1 and the sidewall of the first channel exposed by the first recess has a positive slope with respect to the upper surface of the substrate in claim 2. However, Ohno shows the exposed sidewall being slanted (Fig.7 and [0021]; trench 140 has slanted exposed sidewalls of channel 106) with respect to an upper surface of the substrate and the gate structure is formed to fill the first recess (Fig.1, 10 and [0023]; gate structure 116 formed as a trench gate) and the sidewall of the first channel exposed by the first recess has a positive slope (Fig.7 and [0021]; trench 140 has slanted exposed sidewalls of channel 106) with respect to the upper surface of the substrate. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Kwak by providing the exposed sidewall being slanted with respect to an upper surface of the substrate and the gate structure is formed to fill the first recess in claim 1 and the sidewall of the first channel exposed by the first recess has a positive slope with respect to the upper surface of the substrate in claim 2, as taught by Ohno, so that the trench is designed to include a curved surface or to include a surface including a flat bottom and slanted sidewalls, therefore the second channel layer conform to the surface of the trench [0021] and a gate structure is formed in the trench, where the gate is disposed above and separated from the doped region [0006]. Furthermore, modifying Kwak by incorporating a trench gate structure, as taught by Ohno, would increase the channel length while maintaining device packing density, thereby mitigating problems often associated with short channels.
Regarding claim 6, Kwak discloses after forming the first channel (Fig.2a and [0018, 0037]; epitaxial layer 15 corresponds to a source/drain junction layer formed on the substrate 11,13), forming an etching mask on the first channel, wherein the first etching process includes an isotropic etching process using the etching mask (Fig. 2b and [0024]; region 22 is formed by sequentially etching via a photoetching process using a mask).
Regarding claim 10, Kwak substantially discloses the claimed invention of relates to method for manufacturing transistor including forming an impurity region but is silent about the impurity region includes doping p-type impurities into the substrate. However, Ohno shows forming the impurity region includes doping p-type ([0024]; the source region 122 and the drain region 124 are n-type regions or p-type regions) impurities into the substrate.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Kwak by forming the impurity region includes doping p-type impurities into the substrate, as taught by Ohno, so that the source region and drain regions being a first conductivity type respectively disposed at two sides of the gate structure [0005].
Claim(s) 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak, US 20040108558, in view of Ohno, US 20230012834 as applied to claims 1-2, 6 and 10 above, and further in view of Liao, US 20210391449.
Regarding claims 7 and 9, Kwak in view of Ohno substantially discloses the claimed invention of relates to method for manufacturing transistor including a channel region with first and second channel but is silent about each of the first channel and the second channel includes silicon-germanium in claim 7 and a germanium concentration of the first channel is different from a germanium concentration of the second channel in claim 9. However, Liao shows that each of the first and second channels includes silicon-germanium ([0179] the first channel region including silicon germanium, a second channel region over the first channel region, the second channel region including silicon germanium) and a germanium concentration of the first channel is different ([0179]; the second channel region having a lower germanium concentration than the first channel region) from a germanium concentration of the second channel. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Kwak in view of Ohno by each of the first channel and the second channel includes silicon-germanium in claim 7 and a germanium concentration of the first channel is different from a germanium concentration of the second channel in claim 9, as taught by Liao, so that portions of the channel regions having higher germanium concentrations may be thinned at higher rates than portions of the channel regions having lower germanium concentrations, which may be used to provide channel regions having rectangular profiles. Providing channel regions having more rectangular profiles reduces drain-induced barrier lowering (DIBL), increasing performance and reducing device defects of the resulting semiconductor devices [0010].
Regarding claim 8, Kwak discloses the second channel is formed to contact (Fig.2f and [0031,0034]; channel is formed as epitaxial layer 27 is grown on the semiconductor substrate 11, 13 and on the exposed sidewall of the epitaxial layer 15) the sidewall of the first channel.
Allowable Subject Matter
Claims 3-5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 11-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art does not teach the embodiments claimed in claims 3, 11 and 19, specifically the prior art fails to disclose or render obvious the claimed limitations including after performing the first etching process, performing a second etching process on the first channel and an the first upper portion of the substrate to enlarge a width of the first recess, the first recess as enlarged forming a second recess, as claimed in dependent claim 3, performing a second etching process on the first channel and the first upper portion of the substrate to enlarge a width of the first recess, the first recess as enlarged forming a second recess; performing a second SEG process to form a second channel on a surface of the substrate and a sidewall of the first channel exposed by the second recess; forming a gate structure to fill the second recess, as claimed in independent claim11 and performing a second etching process on the first channel and the first upper portion of the substrate to enlarge a width of the first recess, the first recess as enlarged forming a second recess, and a sidewall of the first channel exposed by the second recess having a negative slope with respect to the upper surface of the substrate; performing a second SEG process to form a second channel on a surface of the substrate and the sidewall of the first channel exposed by the second recess; forming a gate structure to fill the second recess, as claimed in independent claim 19, respectively.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 04/02/2026 have been fully considered but they are not persuasive.
Regarding applicant’s argument about amended claim 1, that the uppermost surface of the substrate contacts the first channel, for example the first channel is above the substrate and contacts the substrate (refer to annotated FIG. 1), however, the specification doesn’t mention/disclose/reference an “uppermost” surface of the substrate, as the examiner couldn’t find the claim language “contacting an uppermost surface of the substrate” in the specification. Also Fig. 2 shows that first channel 120 contacting the uppermost surface of the active pattern 105, not the substrate 100, while active pattern 105 formed on the substrate 100. Therefore, the amended claim language “contacting an uppermost surface of the substrate” is a new matter and the scope of the limitations is unclear and indefinite. Please see the rejection above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW RICHARDS can be reached at (571)272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AZM PARVEZ/
Examiner
Art Unit 2892
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
Prosecution Insights