DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 10 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2024/0121998 to Lee et al (hereinafter Lee).
Regarding Claim 1, Lee discloses a display device comprising:
a substrate including a display area and a non-display area around the display area (Fig. 4);
an upper buffer layer (Fig. 6; 122) on the substrate, the upper buffer layer including at least one inorganic insulating layer [0247];
a first transistor (T1) on the upper buffer layer, the first transistor including a first semiconductor pattern (ACT) and a first gate electrode (GE) on the first semiconductor pattern; and
a first light shielding pattern (LSL) between the substrate and the first transistor, the first light shielding pattern including a metal layer or P-type impurity ions [0173].
Regarding Claim 2, Lee discloses the display device according to Claim 1, wherein the first transistor includes a first oxide semiconductor pattern (ACT) , a first gate electrode (GE) overlapping the first oxide semiconductor pattern, and a first source electrode (ANCH) and a first drain electrode (VDCH), each of the first source electrode and the first drain electrode electrically connected to the first oxide semiconductor pattern,
wherein the first light shielding pattern is electrically connected to one of the first source electrode and the first drain electrode (Fig. 6).
Regarding Claim 3, Lee discloses the display device according to Claim 2, further comprising:
a second transistor (T2) adjacent to the first transistor, the second transistor including a second oxide semiconductor pattern (ACT) on the upper buffer layer, a second gate electrode (GE) overlapping the second oxide semiconductor pattern, and a second source electrode (DCH) and a second drain electrode (not pictured, [0174]), each of the second source electrode and the second drain electrode electrically connected to the second oxide semiconductor pattern, and
wherein the second transistor further includes a second light shielding pattern (LSL) overlapping the second oxide semiconductor pattern, the second light shielding pattern including a metal layer or P-type impurity ions [0173].
Regarding Claim 4, Lee discloses the display device according to Claim 3, wherein the second gate electrode and the second light shielding pattern are electrically interconnected, thereby constituting a dual gate (Fig. 6).
Regarding Claim 5, Lee discloses the display device according to Claim 3, further comprising:
a third transistor on the substrate (T3, Fig. 5), the third transistor comprising:
a third oxide semiconductor pattern on the upper buffer layer; a third gate electrode overlapping the third oxide semiconductor pattern; a third source electrode and a third drain electrode, each of the third source electrode and the third drain electrode electrically connected to the third oxide semiconductor pattern; and a third light shielding pattern overlapping the third oxide semiconductor pattern [0175].
Regarding Claim 10, Lee discloses the display device according to Claim 3, wherein the first light shielding pattern and the second light shielding pattern are on a same layer (Fig. 6).
Regarding Claim 11, Lee discloses the display device according to Claim 5, wherein the first transistor is a driving thin film transistor configured to drive a pixel, and each of the second transistor and the third transistor is a switching thin film transistor (Fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 7, 12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of US PG Pub 2022/0310855 to Tsubuku (hereinafter Tsubuku).
Regarding Claim 6, Lee discloses the display device according to Claim 5, further comprising:
a lower buffer layer (121) including at least one insulating layer disposed on the substrate.
Lee does not explicitly disclose a fourth transistor.
Tsubuku discloses a series of transistors for a display device having transistors in a display area (Fig. 2, 201, 202, 203) and a peripheral area (204) and include four transistors.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have included additional transistors in the circuit of Lee, particularly transistors having polycrystalline silicon as taught by Tsubuku [0027]. Polycrystalline silicon allows for a transistor to function as a light-receiving sensor. Numerous circuits are known in the art and a light sensor in a peripheral region would have been obvious for receiving signals.
Regarding Claim 7, the combination of Lee and Tsubuku makes obvious the display device according to Claim 6, wherein at least a portion of the first light shielding pattern comprises a same material as the polycrystalline semiconductor pattern or the fourth gate electrode of the fourth transistor since gate electrodes commonly use the metals listed by Lee for the light shielding pattern.
Regarding Claim 12, the combination of Lee and Tsubuku makes obvious the display device according to Claim 6, wherein the fourth transistor is in at least one of the non-display area and the display area, and the first transistor is at a pixel of the display area.
Regarding Claim 15, the combination of Lee and Tsubuku makes obvious the display device according to Claim 6, wherein the lower buffer layer has a groove, and includes a metal layer in the groove since Applicant has not noted that the lower buffer layer having a groove or for that group to include a metal layer, solves any particular issue or is included for any noted benefit. Numerous designs for insulation and circuits are known in the art and insulation layers having grooves allow for various design goals such as planarization of the metal and insulating layers.
Claims 8, 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lee and Tsubuku as applied to Claim 6 above, and further in view of US PG Pub 2022/0416001 to Kim et al (hereinafter Kim).
Regarding Claims 8 and 9, the combination of Lee and Tsubuku makes obvious the display device according to Claim 6 but do not disclose the light shielding pattern to comprise multiple layers.
Kim discloses a light shielding pattern having at least a metal pattern and a semiconductor material layer is stacked on the metal pattern [0267].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have formed at least one least one of the light shielding patterns to comprise multiple materials. As noted by Kim, external light reflected may cause incident reflection and a ghost phenomenon. Using multiple layers causes destructive interference of external light thereby preventing or minimizing issues [0268]. Furthermore, it would have been obvious to have a structure wherein the second light shielding pattern has a stacked structure of a metal pattern and a semiconductor material layer, and the third light shielding pattern is constituted by a metal pattern since it would have been obvious to increase the blocking ability of the light blocking layer depending on specific circuit demands.
Regarding Claim 13, the combination of Lee, Tsukuku and Kim makes obvious the display device according to Claim 8, wherein the semiconductor material layer has a reflectivity that is less than a reflectivity of the metal pattern (Kim, [0267].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of US PG Pub 2023/0238389 to Gong et al (hereinafter Gong).
Regarding Claim 16, Lee discloses a display device comprising:
a substrate including a display area and a non-display area around the display area (Fig. 4);
an upper buffer layer (Fig. 6; 122) on the substrate, the upper buffer layer including at least one inorganic insulating layer [0247];
a first transistor (T1) on the upper buffer layer, the first transistor including a first semiconductor pattern (ACT) and a first gate electrode (GE) on the first semiconductor pattern; and
a first light shielding pattern (LSL) between the substrate and the first transistor, the first light shielding pattern including a metal layer or P-type impurity ions [0173].
an upper buffer layer (122) covering the first transistor, the upper buffer layer including at least one inorganic insulating layer;
a second transistor (T2) on the upper buffer layer (see below), the second transistor including a second semiconductor pattern (ACT) and a second gate electrode (GE) on the second semiconductor pattern; and
a second light shielding pattern (LSL) between the substrate and the second transistor, the second light shielding pattern including a metal layer or P-type impurity ions [0173].
Lee does not explicitly disclose the two transistors to be on different buffer layers and therefore different levels. However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have formed the transistors on different levels as seen in Gong, Fig. 1. Transistors can be formed on different layers for numerous reasons such as providing distance between electrical components, thereby avoiding parasitic capacitance and/or to allow for additional elements be formed above or below the transistors. Absent any unexpected results by Applicant, it would have been obvious to form transistors on different buffer layers and different stacked levels for at least the reasons above.
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 14 requires the display device according to claim 8, wherein the polycrystalline semiconductor pattern and the semiconductor material layer are doped with P-type impurity ions. The references of record do not disclose doping the semiconductor material layer of the light blocking layer with p-type impurity ions. It is not apparent that the light blocking layer would benefit from such a modification or function equally as well.
Conclusion
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893