1DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election, with traverse, of group I, claims 1-21, in ”Response to Election / Restriction Filed -12/08/2025”, is acknowledged.
Applicant’s traversal arguments, in “Remarks - 12/08/2025 - Applicant Arguments/Remarks Made in an Amendment”, on the ground that ‘examination of the claims of each of the Groups is not believed to create an undue burden on the Office”. However, this is not persuasive since "The searches for the device and process inventions are not co-extensive and are distinct for product and process in the distinct area of examination”.
Applicant general statement “the USPTO has historically examined applications containing multiple sets of claims with different sub-classifications” is not applicable for this application, and every case is different.
For the restriction requirement, the distinction of invention can be sufficiently evaluated from classification and subject matter of independent claims, which were done. The comparison of all claims will defeat the very basic concept of reducing the burden issue of examination. For example, for this application, if “MPEP § 806.05(f)’s path 1 i.e. “The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product” is followed, the process steps of claims 23 are not required to make any product of claims in group I, and so on.
The requirement is still deemed proper , and is therefore made FINAL, and thus the required provisional election (see MPEP § 818.03(b)) becomes an election without traverse.
In view of the above, this office action considers claims 1-30 pending for prosecution, of which, non-elected claims 22-30 are withdrawn, and elected claims 1-21 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 1A; [0022] or C 18, L 18-37)= (element 100; Figure No. 1; Paragraph No. [0022]) or Column No 18, Line Nos. 18-17. For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” or “Column No, Line Nos" shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-11, 13-19 and 21 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by LIM; Seok Ling et al., (US 20220068764 A1) hereinafter Lim
Regarding Claim 1. Lim teaches an integrated circuit (IC) device (a device 100; Figs 1A-1B; [0022]) comprising: (see the entire document, Figs 1A-1B, 4A-4G, along with subject matter referenced in other figures, specifically, as cited below):
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Lim Figure 1B and Figure 1A
a substrate (106, labelled as interposer; Figure 1A, [0025]; detailed in Fig 4A; [0072]) comprising a first side (bottom in Fig 1A-1B, top in Fig 4A) having a stepped configuration (Fig 4B with recess 428) having a first surface (bottom/top of 106/406; Figs 1A/4B) that is elevated relative to a second surface (bottom of recess 428; Fig 4B; [0073]; depicted top of recess 128 in fig 1A; [0033]);
a first set of solder balls (108, labelled as plurality of bumps; Fig 1A-1B; [0026]) electrically connected to a first set of contacts (112; Fig 1B) in first solder resist openings (SROs) (opening in 122 that accommodates 108; hereinafter 108_SROs) in the first surface (of 106/406), wherein a solder ball (108) of the first set of solder balls has a first characteristic dimension (the characteristic dimension is a largest dimension of the solder ball parallel to the contact 112; say 80 μm; [0026]); and
a second set of solder balls (110, labelled as plurality of bumps; Fig 1A-1B; [0027]) electrically connected to a second set of contacts (112) in second SROs (opening in 122 that accommodates 108; hereinafter 110_SROs) in the second surface (of recess 428; Fig 4B), wherein a solder ball of the second set of solder balls has a second characteristic dimension (the characteristic dimension is a largest dimension of the solder ball parallel to the contact 112; say 200 μm; [0027]) larger (because 200 μm is larger than 80 μm) than the first characteristic dimension.
Regarding Claim 2. Lim as applied to the IC device of claim 1, further teaches, wherein distal ends (that touches surface/contact of 102; Fig 1A) of solder balls (108) of the first set of solder balls are coplanar (Fig 1B) with distal ends (that touches surface/contact of 102; Fig 1A) of solder balls (110) of the second set of solder balls (110).
Regarding Claim 3. Lim as applied to the IC device of claim 2, further teaches, wherein (Fig 1A) sizes of solder balls of the first set of solder balls (108) and the second set of solder balls (110) and sizes of the first SROs (108_SROs) and the second SROs (110_SROs) facilitate coplanarity (depicted in Fig 1A) of the distal ends of solder balls of the first set of solder balls with the distal ends of solder balls of the second set of solder balls.
Regarding Claim 4. Lim as applied to the IC device of claim 1, further teaches, (the device) further comprising at least one landside component (LSC) (118; Fig 1A; [0035-0036]) electrically connected to one or more interconnects in the second surface (top of 128; Fig 1A).
Regarding Claim 5. Lim as applied to the IC device of claim 1, further teaches, wherein centers of adjacent first SROs (108_SROs) are separated by a first pitch distance, and wherein centers of adjacent second SROs (110_SROs) are separated by a second pitch distance larger (depicted in Fig 1B, further supported by larger dimeter of 110) than the first pitch distance.
Regarding Claim 6. Lim as applied to the IC device of claim 1, further teaches, (the device) further comprising a circuit board (102; [0020] The package substrate 102 may be connected to a motherboard (not shown) through the plurality of solder balls 104. The motherboard may be a PCB.) electrically connected to the substrate via the first set of solder balls and the second set of solder balls.
Regarding Claim 7. Lim as applied to the IC device of claim 1, further teaches, (the device) further comprising a second IC device (124; Fig 1A; [0039]) electrically connected to the first set of solder balls (108 through TSV 112 for signals) and the second set of solder balls (110 through TSV 114 for power).
Regarding Claim 8. Lim as applied to the IC device of claim 1, further teaches, wherein the first surface (bottom/top of 106/406; Figs 1A/4B) is disposed about a perimeter (depicted in Fig 4B and construed from [0073]: a recess 428 formed in the interposer 406 using mechanical drilling and/or laser drilling) of the second surface (bottom/top of recess 128/428; Figs 1A/4B).
Regarding Claim 9. Lim as applied to the IC device of claim 8, further teaches, (the device) further comprising a die (124B; Fig 1A-1B; [0038-0039]) electrically coupled to a second side (top of 106 in Fig 1A) of the substrate (106_, wherein the second surface (top of recess 128 in fig 1A; is located in a die shadow of the die (124B).
Regarding Claim 10. Lim as applied to the IC device of claim 9, further teaches, wherein at least one solder ball (110) of the second set of solder balls is electrically connected (Through TSV 114) to a power delivery network configured to provide power to the die (124b; [0039-0040] the plurality of second TSVs 114 may be configured to transmit power between the package substrate 102 and the semiconductor device 124).
Regarding Claim 11. Lim as applied to the IC device of claim 9, further teaches, wherein at least one solder ball of the second set of solder balls (110) is an input/output (I/O) interconnection ([0039]).
Regarding Claim 13. Lim as applied to the IC device of claim 1, further teaches, wherein the substrate (106) comprises a first count (at least 4 of 112; Fig 1a) of metal layers (112) between a second side (top of 106 in Fig 1A) of the substrate (106) and the first surface (bottom of 106 in Fig 1A) of the first side (bottom of 106 in Fig 1A), wherein the substrate (106) comprises a second count (two of 114) of metal layers (114) between the second side (top of 106 in Fig 1a) and the second surface (top of recess 128 in fig 1a) of the first side, and wherein the first count (at least 4) is greater than the second count (2).
Regarding Claim 14. Lim teaches a device (a device 100; Figs 1A-1B; [0022]) comprising: (see the entire document, Figs 1A-1B, 4A-4G, along with subject matter referenced in other figures, specifically, as cited below):
a substrate (106, labelled as interposer; Figure 1A, [0025]; detailed in Fig 4A; [0072]) comprising a first side (bottom in Fig 1A-1B, top in Fig 4A) having a stepped configuration (Fig 4B with recess 428) having a first surface (top of 106/406; Figs 1A/4B) that is elevated relative to a second surface (bottom of recess 428; Fig 4B; [0073]; depicted as top of recess 128 in Fig 1A; [0033]);
a first set of solder balls (108, labelled as plurality of bumps; Fig 1A-1B; [0026]) electrically connected to a first set of contacts (112; Fig 1B) in first solder resist openings (SROs) (opening in 122 that accommodates 108; hereinafter 108_SROs) in the first surface (of 106/406), wherein a solder ball (108) of the first set of solder balls has a first characteristic dimension (the characteristic dimension is a largest dimension of the solder ball parallel to the contact 112; say 80 μm; [0026]);
a second set of solder balls (110, labelled as plurality of bumps; Fig 1A-1B; [0027]) electrically connected to a second set of contacts (112) in second SROs (opening in 122 that accommodates 108; hereinafter 110_SROs) in the second surface (of recess 428; Fig 4B), wherein a solder ball of the second set of solder balls has a second characteristic dimension (the characteristic dimension is a largest dimension of the solder ball parallel to the contact 112; say 200 μm; [0027]) larger (because 200 μm is larger than 80 μm) than the first characteristic dimension.
a die (124A; Fig 1A-1B; [0038-0039]) electrically connected to a second side (top of 106 in Fig 1A) of the substrate (106);
a mold (122) compound coupled to the second side and at least partially encapsulating the die; and
a second substrate (102; Fig 1A; [0029]) coupled to the mold compound (122), wherein the second substrate (102) comprises a third set of contacts (not labelled but depicted in Fig 1A underlying 110) configured to be electrically connected ([0038]) to a fourth set of contacts (126) of a second device (124B).
Regarding Claim 15. Lim as applied to the device of claim 14, further teaches, wherein centers of adjacent first SROs (108_SROs) are separated by a first pitch distance, and wherein centers of adjacent second SROs (110_SROs) are separated by a second pitch distance larger (depicted in Fig 1B, further supported by larger dimeter of 110) than the first pitch distance.
Regarding Claim 16. Lim as applied to the device of claim 14, further teaches, (the device) further comprising the second device electrically connected to the third set of contacts of the second substrate, wherein the second device comprises dynamic random-access memory (DRAM) ([0034] A memory device which may be a DRAM [0083]).
Regarding Claim 17. Lim as applied to the device of claim 14, further teaches, (the device) further comprising a circuit board (102; [0020] The package substrate 102 may be connected to a motherboard (not shown) through the plurality of solder balls 104. The motherboard may be a PCB.) electrically connected to the substrate via the first set of solder balls and the second set of solder balls.
Regarding Claim 18. Lim as applied to the device of claim 14, further teaches, wherein distal ends (that touches surface/contact of 102; Fig 1A) of solder balls (108) of the first set of solder balls are coplanar (Fig 1B) with distal ends (that touches surface/contact of 102; Fig 1A) of solder balls (110) of the second set of solder balls (110).
Regarding Claim 19. Lim as applied to the device of claim 1, further teaches, wherein the first surface (bottom/top of 106/406; Figs 1A/4B) is disposed about a perimeter (depicted in Fig 4B and construed from [0073]: a recess 428 formed in the interposer 406 using mechanical drilling and/or laser drilling) of the second surface (bottom/top of recess 128/428; Figs 1A/4B).
Regarding Claim 21. Lim as applied to the device of claim 1, further teaches, (the device) further comprising at least one landside component (LSC) (118; Fig 1A; [0035-0036]) electrically connected to one or more interconnects in the second surface (top of 128; Fig 1A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over LIM; Seok Ling et al., (US 20220068764 A1) hereinafter Lim; in view of LEUTEN; Tyler et al., (US 20180182735 A1) hereinafter Leuten.
Regarding Claim 12, 20 Lim as applied to the IC device of claim 1 and/or device of claim 14 , does not expressly disclose, wherein the second surface (top of recess 128; Fig 1A) is disposed about a perimeter of the first surface (bottom of 106; Fig 1A).
.However, in the analogous art Leuten teaches BGA packages with a LGA package extension with various configuration ([Abstract]), wherein Figure 6D is analogous to Lim’s Fig 1A cited for claims 1/14 rejection above; and Figure 6E in paragraph [0044] teaches a configuration, wherein the second surface (top of recess of 505) is disposed about a perimeter of the first surface (bottom of 505). The sectional view shown in FIG. 6E is along the dashed A-A′ line denoted in FIG. 5. As shown in FIG. 6E, component 505 includes non-planar package substrate 675. In this embodiment, a center portion of substrate 675 is proud of a perimeter or edge portion of substrate 675. Extension component 425 is located at the edge recesses of package substrate 675. Solder feature 620 electrically interconnects extension component 425 to substrate 201, and solder features 630 electrically interconnect extension component 425 to component 505. This configuration is suitable to distribution along a perimeter of the package assemble.
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Leuten Figure 6D Figure 6E
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to adopt Leuten’s configuration of Fig 6E for Lim’s device, and thereby the combination of (Lim and Leuten) device comprises the second surface (top of recess in view of Leuten) is disposed about a perimeter of the first surface (bottom of 106 in view of Leuten Fig 6E), since this configuration added benefit for low volume assembly and is suitable to distribution along a perimeter of the package assemble (Leuten [0044])).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
February 19, 2026