DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s arguments, see pages 5 and 6, filed 05/14/2026, with respect to applicant’s amendment to claim 1 have been fully considered and are persuasive. The restriction requirement of 04/07/2026 has been withdrawn.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “fixing unit configured to fix the rotation driving unit and the wafer support unit, such that the wafer support unit is rotated through the fixing unit” of claim 2, “fixing unit is configured to fix the wafer support unit by adsorbing the wafer support unit against the rotation driving unit” of claim 3, “the fixing unit is configured to fix the wafer support unit and the rotation driving unit using vacuum adsorption or magnetic adsorption” of claim 4, and "flat zone of each wafer" of claims 12 & 16 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Examiner notes that the wafer support unit is only shown in figure 3 on its own with no relationship to the fixing unit shown.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“a gas supply unit” in claim 1 which corresponds to openings in the sidewall in figure 1
“a rotation driving unit” in claims 1 and 11 which is disclosed as “a turn-table like structure” in paragraph [0048] of the specification
“a wafer support unit” in claims 1 and 11 which has been disclosed as “a quartz boat” in paragraph [0048] of the specification
“a gas release unit” in claim 1 which corresponds to openings in the sidewall in figure 1
“a fixing unit” in claim 2 which is disclosed as utilizing vacuum absorption or magnetic absorption in paragraph [0049] of the specification
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 and 16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 12 and 16, “a flat zone of each wafer on one side of each wafer” of claim 12 and “a flat zone of each wafer” of claim 16 are unclear about if the “flat zone” is a planar face of a wafer or if it refers to a flat portion of the sidewall of a wafer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 6-11, 15, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiera et al. (US 2017/0107620 A1) in view of Klostermann et al. (US 2005/0087519 A1).
Regarding claim 1, Sugiera discloses a wafer processing apparatus (Sugiera 202) comprising:
A gas supply unit (Sugiera 234) located on one side of the wafer processing apparatus (see Sugiera figure 1) and configured to supply high-temperature gases to transfer heat to wafers loaded inside the wafer processing apparatus (Sugiera [0022], “A gas pipe heater 22 configured to heat the gas pipe 10 is installed around the gas pipe 10 extending from the gas supply part 4 to the process chamber 201”);
A rotation driving unit (Sugiera 267 and 321, Examiner notes that controller 321 controls various systems including the rotation mechanism , see Sugiera figure 2) comprising a rotation controller (Sugiera 321, see figure 2) and configured to rotate a wafer support unit (Sugiera 217) including the wafers (Sugiera 200); and
A gas release unit (Sugiera 231, 243, and 246) located on the other side of the wafer annealing apparatus (see Sugiera figure 1) and configured to release the high temperature gas fed to the wafer processing apparatus (Sugiera [0053], “According to the present embodiment, the precursor (HCDS) gas is supplied from the gas pipe 10 into the process chamber 201 while heating the gas pipe 10 with at least the gas pipe heater 22. The raw material gas is exhausted 55263from the process chamber 201 through the exhaust pipe 231. It is therefore possible to reduce temperature unevenness in the gas pipe 10 and the exhaust pipe 231.”),
Wherein the rotation controller (Sugiera 321) comprises at least one processor (Sugiera 321a). Examiner notes that Sugiera is focused on a process for fil formation on a wafer but discloses the apparatus can also be utilized for an annealing process (Sugiera [0114], “In the aforementioned embodiments, there has been described an example in which the film is formed on the wafer. However, the present disclosure is not limited to this example. For example, the present disclosure may be applied to a case where an oxidation process, a diffusion process, an annealing process, an etching process or the like is performed with respect to the wafer or a film formed on the wafer”).
Sugiera is silent regarding controlling the rotation driving unit to rotate a wafer 180 degrees after the high-temperature gases are supplied for a preset period of time to transfer heat to the wafers.
However, Klostermann teaches a method (Klostermann 200) for annealing a wafer comprising steps of supplying high heat to a wafer (Klostermann 230) and then rotating the wafer to a different predetermined angle (Klostermann 255, [0058], “the wafer could be rotated a predetermined angle (e.g., 45, 90 degrees etc.) to process the individual wafer (or a different spot on the wafer) differently”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify Sugiera’s apparatus by incorporating Klostermann’s teachings of rotating the wafer to a different angle, and given the limited number of possible angles it would have been obvious to try an angle of 180 degrees to produce a predictable result of allowing embedded modules to be rotated in different directions (Klostermann [0058], “Another application would be for providing different module orientations in embedded (e)-DRAMS design and the like. That is, the DRAM designer may want the embedded modules to be rotated in a certain manner (e.g., 90 degrees). The local annealing would provide much flexibility in the DRAM design to the DRAM designer/engineer”).
Regarding claim 2, Sugiera and Klostermann as applied to claim 1 teach the wafer support unit (Sugiera 217) is secured to the rotation driving unit by a fixing unit (Sugiera quartz cap 218), such that the wafer support unit is rotated through the fixing unit (Sugiera [0026], “the boat 217 held on the quartz cap 218 is rotated by rotating the rotating mechanism 267”).
Regarding claim 6, Sugiera and Klostermann as applied to claim 1 are silent regarding the preset period of time being determined by temperature.
However, Klostermann further teaches that the time required for annealing is a function of time (see Klostermann figure 3, [0061], “FIG. 3A shows a graph 300 with the typical anneal times as a function of temperature. As the temperature increases, the time required for the anneal decreases. The current typical temperatures and the time required is shown at reference numeral 310”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify Sugiera’s apparatus to utilize a preset time period for the heating step determined by the temperature of the gases to produce a predictable result of annealing for the appropriate amount of time for the given temperature to improve overall quality of the wafers.
Regarding claim 7, Sugiera and Klostermann as applied to claim 1 further teach a temperature measure unit including a temperature sensor (555) configured to measure a temperature of the high-temperature gases (Sugiera [0062], “Since the surface area of the major surface of the temperature sensing pan 555 facing the gas pipe 10 is large, it is easy for the temperature sensing part 555 to sense the thermal state of the gas pipe 10 and to accurately detect the temperature of the gas pipe 10”) and transmit information on the measured temperature to the rotation controller (see Sugiera figure 2).
Regarding claim 8, Sugiera and Klostermann as applied to claim 1 teach the high-temperature gases that have transferred heat to the wafers in the wafer support unit are released through the gas release unit (Sugiera [0041], “At step S1, the HCDS gas is supplied. Initially, the valve 34 installed in the gas pipe 10 and the APC valve 243 installed in the exhaust pipe 231 are opened. The HCDS gas, which is supplied from the gas supply part 4 and flow-rate-adjusted by the flow rate controller 41, is allowed to flow through the gas pipe 10 and is supplied from the gas supply holes of the nozzle 234 into the process chamber 201. The HCDS gas is exhausted from the exhaust pipe 231. At this time, the as pipe heater 22 heats the gas pipe 10 and the exhaust pipe heater 20 heats the exhaust pipe 231”).
Regarding claim 9, Sugiera and Klostermann as applied to claim 8 further teach the controller is configured to control an internal pressure by controlling the high temperature gases released from the gas release unit (Sugiera [0032], “The CPU 321a is configured to, according to the content of the process recipe thus read, control the flow rate adjusting operations of various kinds of gases performed by the flow rate controllers 32, 33 and 41, the opening/closing operations of the valves 34, 35, 36 and 39, the opening/closing operation of the APC valve 243, the pressure regulating operation performed by the APC valve 243 based on the pressure sensor 245”) utilizing a pressure sensor (Sugiera 245).
Regarding claim 10, Sugiera and Klostermann as applied to claim 9 are silent regarding the exact location of the pressure controller within the wafer annealing apparatus.
However, applicant is silent regarding any significance to the placement of the pressure controller and a court has held that a rearrangement of parts known in the prior art that does not modify functionality is an obvious matter of design choice. (see MPEP § 2144.04 VI C)
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify Sugiera’s apparatus by selecting a location facing the rotation driving unit for the pressure controller since the exact location within the pressure-controlled environment does not alter functionality of the controller.
Regarding claim 11, Sugiera discloses a method for processing wafers comprising:
Loading a wafer support unit (Sugiera 217) including wafers (Sugiera 200) onto a rotation driving unit of a wafer processing apparatus (Sugiera [0026], “The boat 217 can be loaded into and unloaded from the process chamber 201 by a boat elevator used as a boat elevator mechanism, A rotating mechanism 267 used as a boat rotating mechanism, which is a rotating means for rotating the boat 217, is installed to improve the processing uniformity”);
Sugiera discloses that the apparatus can be used for an annealing process (Sugiera [0114], “For example, the present disclosure may be applied to a case where an oxidation process, a diffusion process, an annealing process, an etching process or the like is performed with respect to the wafer or a film formed on the wafer.”).
However, Klostermann teaches a method (Klostermann 200) for annealing a wafer comprising steps of supplying high heat to a wafer (Klostermann 230) for a first annealing step and then rotating the wafer to a different predetermined angle (Klostermann 255, [0058], “the wafer could be rotated a predetermined angle (e.g., 45, 90 degrees etc.) to process the individual wafer (or a different spot on the wafer) differently”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify Sugiera’s apparatus by incorporating Klostermann’s teachings of rotating the wafer to a different angle, and given the limited number of possible angles it would have been obvious to try an angle of 180 degrees to produce a predictable result of allowing embedded modules to be rotated in different directions (Klostermann [0058], “Another application would be for providing different module orientations in embedded (e)-DRAMS design and the like. That is, the DRAM designer may want the embedded modules to be rotated in a certain manner (e.g., 90 degrees). The local annealing would provide much flexibility in the DRAM design to the DRAM designer/engineer”).
Regarding claim 15, Sugiera and Klostermann as applied to claim 11 further teach further teach the controller is configured to control an internal pressure by controlling the high temperature gases released from the gas release unit (Sugiera [0032], “The CPU 321a is configured to, according to the content of the process recipe thus read, control the flow rate adjusting operations of various kinds of gases performed by the flow rate controllers 32, 33 and 41, the opening/closing operations of the valves 34, 35, 36 and 39, the opening/closing operation of the APC valve 243, the pressure regulating operation performed by the APC valve 243 based on the pressure sensor 245”) utilizing a pressure sensor (Sugiera 245).
Regarding claim 17, Sugiera and Klostermann as applied to claim 11 are silent regarding the preset period of time being determined by temperature.
However, Klostermann further teaches that the time required for annealing is a function of time (see Sugiera figure 3, [0061], “FIG. 3A shows a graph 300 with the typical anneal times as a function of temperature. As the temperature increases, the time required for the anneal decreases. The current typical temperatures and the time required is shown at reference numeral 310”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify Sugiera’s method to utilize a preset time period for each annealing step determined by the temperature of the gases to produce a predictable result of annealing for the appropriate amount of time for the given temperature to improve overall quality of the wafers.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiera et al. (US 2017/0107620 A1) and Klostermann et al. (US 2005/0087519 A1) as applied to claim 2 above, and further in view of Aida (US 2023/0063662 A1).
Regarding claim 3, Sugiera and Klostermann as applied to claim 2 are silent regarding how the fixing unit and wafer support unit are fixed.
However, Aida teaches a substrate processing apparatus (Aida 1) comprising a wafer support unit (Aida 12) secured to a rotation driving unit (Aida 13) secured together by a fixing unit (Aida 14d) that utilizes vacuum adsorption to secure the wafer support unit against the rotation driving unit (Aida [0054], “The vacuum chuck 14d fixes the position of the substrate holding unit 12 in the plane direction of the wafer W with respect to the rotation support unit 11.”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify Sugiera’s apparatus to incorporate Aida’s teachings of a fixing unit utilizing vacuum adsorption to produce a predictable result of securing the rotation driving unit and wafer support unit together without requiring tools.
Regarding claim 4, Sugiera, Klostermann, and Aida as applied to claim 3 teach the fixing unit is configured to use vacuum adsorption (Aida [0054], “The vacuum chuck 14d fixes the position of the substrate holding unit 12 in the plane direction of the wafer W with respect to the rotation support unit 11.”).
Claim(s) 12 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiera et al. (US 2017/0107620 A1) and Klostermann et al. (US 2005/0087519 A1) as applied to claim 11 above, and further in view of Prengle (US 2021/0159111 A1).
Regarding claim 12, Sugiera and Klostermann as applied to claim 11 are silent regarding the annealing step comprising locating a flat zone of each wafer.
However, Prengle teaches a wafer annealing apparatus (Prengle 100) comprises a wafer alignment unit (Prengle 230) configured to rotate wafers into a direction suitable for annealing (Prengle [0057], “The alignment unit 230 is a processing unit rotating the semiconductor wafer W in a horizontal plane to orient the semiconductor wafer W in a direction suitable for flash heating”) by locating a flat zone for orientation (Prengle [0057], “a mechanism to optically detect any notch or orientation flat formed at the periphery of the semiconductor wafer W, and the like).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the method for annealing to incorporate Prengle’s teachings of locating a flat zone used for orientation to produce a predictable result of allowing proper alignment of wafers for annealing to improve overall quality of the produced wafers.
Regarding claim 16, Sugiera and Klostermann as applied to claim 11 are silent regarding rotating the wafer support unit so that a flat zone of each wafer is located on the other side of each wafer to which the high temperature gases are supplied.
However, Prengle teaches a wafer annealing apparatus (Prengle 100) comprises a wafer alignment unit (Prengle 230) configured to rotate wafers into a direction suitable for annealing (Prengle [0057], “The alignment unit 230 is a processing unit rotating the semiconductor wafer W in a horizontal plane to orient the semiconductor wafer W in a direction suitable for flash heating”) by locating a flat zone for orientation (Prengle [0057], “a mechanism to optically detect any notch or orientation flat formed at the periphery of the semiconductor wafer W, and the like).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the method for annealing to incorporate Prengle’s teachings of locating a flat zone used for orientation to produce a predictable result of allowing proper alignment of wafers for annealing to improve overall quality of the produced wafers. Examiner notes that if the wafer is aligned to the flat zone before the first annealing step then the rotation step will result in the flat zone being located on an other side after rotation is completed.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiera et al. (US 2017/0107620 A1) and Klostermann et al. (US 2005/0087519 A1) as applied to claim 11 above, and further in view of Yoneda (US 5,648,282).
Regarding claim 13, Sugiera and Klostermann as applied to claim 11 are silent regarding the annealing step including a main annealing step and an additional annealing step.
However, Yoneda teaches an annealing method (see Yoneda figure 6) comprising a main annealing step and a second annealing step in different gases (see Yoneda figure 6) intended to prevent diffusion of impurities (Yoneda column 14 lines 37-45, “For this reason, it is possible that the impurity deported the cell plate 143 may diffuse itself beneath the gate insulating layer at the initial stage of formation of the gate insulating layer 148 on the gate of the MOS transistor or a selector switch. To avoid this, a thermal treatment sequence as shown in FIG. 6 is carried out”).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the method to incorporate Yoneda’s teachings of a two step annealing processing utilizing different temperatures and gas mixtures to produce a predictable result of preventing diffusion of impurities to improve the quality of the produced wafers.
Regarding claim 14, Sugiera, Klostermann, and Yoneda as applied to claim 13 are silent regarding the main annealing step being performed at a temperature of 330 to 360 degrees Celsius and the additional annealing step being performed at a temperature of 390 to 410 degrees Celsius.
However, Klostermann further teaches that the time required for annealing is a function of time (see Klostermann figure 3, [0061], “FIG. 3A shows a graph 300 with the typical anneal times as a function of temperature. As the temperature increases, the time required for the anneal decreases. The current typical temperatures and the time required is shown at reference numeral 310”) and further teaches the preferred temperature range is 300 to 500 degrees Celsius (Klostermann [0041]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the method to select temperatures within the ranges of 330 to 360 degrees Celsius for the main annealing step and 390 to 410 degrees Celsius for the additional annealing step to produce a predictable result of annealing at an appropriate temperature to produce acceptable wafers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES R BRAWNER whose telephone number is (571)272-0228. The examiner can normally be reached Monday - Friday 8:00am - 4:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helena Kosanovic can be reached at (571) 272-9059. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLES R BRAWNER/Examiner, Art Unit 3762
/HELENA KOSANOVIC/Supervisory Patent Examiner, Art Unit 3762
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