DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Jun. 12th 2026 has been entered. Claims 1-12 remain pending in the application. Applicant’s amendments to the Specification (Title) have overcome each and every objection previously set forth in the Non-Final Office Action mailed on Jan. 13th 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US 20210183862) in view of Kang et al. (US 20170186753) and Xiang et al. (US 6586808 from IDS).
Regarding claim 1, Son teaches a semiconductor device (Abstract) comprising:
a horizontal layer (fig. 3, semiconductor patterns SP; para. 0037) spaced apart from a lower structure (substrate SUB; para. 0035) to extend along a direction (second direction D2; para. 0037) parallel to the lower structure (SUB);
a first conductive line (bit lines BL; para. 0031) extending along a direction (third direction D3; para. 0031) perpendicular to the lower structure (SUB) and coupled to one end of the horizontal layer (SP);
a data storage element (data storage element DS) coupled to the other end of the horizontal layer (SP); and
a second conductive line (word lines WL; para. 0032) extending along a direction (first direction D1; para. 0032) across the horizontal layer (SP),
wherein the second conductive line (WL) comprises:
a generic gate (first gate electrode GE1 or second gate electrode GE2) positioned adjacent to the first conductive line (GE1 positioned adjacent to BL though first dopant region SD1; para. 0038).
Son fails to explicitly teach the generic gate comprises:
a high work function electrode; and
a low work function electrode having a cup shape laterally oriented and positioned adjacent to the first conductive line and having a lower work function than the high work function electrode.
However, Kang teaches the generic gate (Kang: fig. 10B, gate electrode BG2; para. 0168, similar to GE1 of Son) comprises:
a high work function electrode (Kang: lower buried portion 307 is formed of a material having a higher work function; para. 0151); and
a low work function electrode (Kang: work function liner 310L may have a work function lower; para. 0152) having a cup shape laterally oriented (Kang: U-shape and view laterally as the horizontal GE1 of Son) and positioned adjacent to the first conductive line (Kang: first impurity region 313; para. 0152, similar to SD1 connect to BL of Son) and having a lower work function (Kang: 310L includes lower work function material) than the high work function electrode (Kang: 307 includes higher work function material).
Kang and Son are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a high work function electrode and a low work function electrode for the generic gate as taught by Kang.
Doing so would realize gate structure with intermediate barrier to improve insulation internal pressure between the gate electrode and other conductive structures and improved performance (Kang: para. 0009, 0184).
Son in view of Kang fails to teach an additional low work function electrode adjacent to the data storage element and having a lower work function than the high work function electrode,
wherein the low work function electrode and the additional low work function electrode are physically separated from each other by the high work function electrode.
However, Xiang teaches an additional low work function electrode (Xiang: fig. 1, right lateral gate electrode portion 34b; col. 4, lin. 24-25) and having a lower work function (Xiang: 34a has higher work function than 34b; col. 4, lin. 34-35) than the high work function electrode (Xiang: center gate electrode portion 34a; col. 4, lin. 23-24),
wherein the low work function electrode (Xiang: left 34b) and the additional low work function electrode (Xiang: right 34b) are physically separated from each other by the high work function electrode (Xiang: 34a).
Xiang, Kang and Son are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add additional low work function electrode as taught by Xiang.
Doing so would realize dual work function gates to improve control over the channel so as to reduce device performance degradation caused by short channel effects (Xiang: col. 3, lin. 47-50).
Regarding claim 2, Son in view of Kang and Xiang further teaches the semiconductor device of claim 1, further comprising:
a covered barrier layer (Kang: fig. 10B, lower barrier 311; para. 0150) covering an upper surface (Kang: right surface as upper surface when view as the horizontal GE1 in Son), a lower surface (Kang: left surface), and one side surface (Kang: bottom surface) of the high work function electrode (Kang: 307); and
a vertical barrier layer (Kang: intermediate barrier 312; para. 0150 and vertical when view as the horizontal GE1 in Son) between the other side surface (Kang: top surface) of the high work function electrode (Kang: 307) and the low work function electrode (Kang: 310L).
Regarding claim 3, Son in view of Kang and Xiang further teaches the semiconductor device of claim 1, wherein the low work function electrode (Kang: fig. 10B, 310L) includes an outer surface (Kang: bottom surface) opposed to the high work function electrode (Kang: 307) and a bended inner surface (Kang: top surface bended U-shape) opposed to the first conductive line (Kang: connect to 313).
Regarding claim 4, Son in view of Kang and Xiang further teaches the semiconductor device of claim 3, further comprising:
a gap-fill material (Kang: fig. 10B, upper buried portion 308M; para. 0168) disposed on the inner surface (Kang: top surface) of the low work function electrode (Kang: 310L).
Regarding claim 5, Son in view of Kang and Xiang further teaches the semiconductor device of claim 1, further comprising:
a gap-fill material (Kang: fig. 10B, upper buried portion 308M; para. 0168) disposed on an inner surface (Kang: top surface) of the low work function electrode (Kang: 310L).
Regarding claim 6, Son in view of Kang and Xiang further teaches the semiconductor device of claim 1, wherein the low work function electrode (Kang: fig. 10B, 310L) includes N-type dopant doped polysilicon (Kang: 310L includes N-type doped polysilicon; para. 0152).
Regarding claim 7, Son in view of Kang and Xiang further teaches the semiconductor device of claim 1, wherein the high work function electrode (Kang: fig. 10B, 307) includes metal, metal nitride (Kang: 307 may include tungsten; para. 0168), or a combination thereof.
Regarding claim 8, Son in view of Kang and Xiang further teaches the semiconductor device of claim 1, wherein the horizontal layer (Son: fig. 3, SP) includes a single crystal semiconductor material, a polycrystalline semiconductor material (Son: poly-silicon and/or single-crystalline silicon; para. 0037), or an oxide semiconductor material.
Regarding claim 9, Son in view of Kang and Xiang further teaches the semiconductor device of claim 1, wherein the horizontal layer (Son: fig. 3, SP) comprises:
a first doped region (Son: first dopant region SD1; para. 0038) coupled to the first conductive line (Son: BL);
a second doped region (Son: second dopant region SD2; para. 0038) coupled to the data storage element (Son: DS); and
a channel (Son: channel region CH; para. 0038) between the first doped region (Son: SD1) and the second doped region (Son: SD2).
Regarding claim 10, Son in view of Kang and Xiang further teaches the semiconductor device of claim 1, wherein the second conductive line (Son: fig.3, WL) includes a double structure (Son: GE1 and GE2) and opposed to each other (Son: SP between GE1 and GE2) with the horizontal layer (Son: SP) interposed therebetween.
Regarding claim 11, Son in view of Kang and Xiang further teaches the semiconductor device of claim 1, wherein the data storage element (Son: fig. 8A, DS) includes a capacitor (Son: capacitor; para. 0033), and the capacitor (Son: capacitor DS) includes a cylindrical first electrode (Son: first electrode EL1 may have a solid cylinder shape; para. 0073), a second electrode (Son: second electrode EL2; para. 0073), and a dielectric layer (Son: dielectric layer DL; para. 0073) between the first electrode (Son: EL1) and the second electrode (Son: EL2).
Regarding claim 12, Son in view of Kang and Xiang further teaches the semiconductor device of claim 1, further comprising:
a gate dielectric layer (Son: fig. 8A, gate insulating layer GI; para. 0061) fully covering each of an upper surface and a lower surface of the horizontal layer (Son: upper surface and lower surface of SP).
Response to Arguments
Applicant’s arguments with respect to claims 1-12 of prior art rejections (35 USC 102/103) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
Prosecution Insights