DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendments to claims 2-4 filed on 4/28/2026 are acknowledged and have since been entered. The rejection of claims 2-4 under 35 U.S.C. 112(b) set forth in the previous Office action is withdrawn.
Response to Arguments
Applicant’s arguments filed on 4/28/2026 with respect to claim 1-2 and 4-17 under 35 U.S.C. 103 over Vinciarelli in view of Rogers have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Vinciarelli and Stessin as shown in the following 103 rejection session.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Vinciarelli et. al ( US-9269661-B1, hereinafter Vinciarelli), and further in view of Stessin et.al. (WO-2013/179205-A1, hereinafter Stessin)
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Regarding Claim 1.
Vincairelli teaches An electrical power switch, the power switch comprising:
an array of rows and columns of transistors, each transistor having a source, drain, and gate (See Vinciarelli Fig,9A-9B, gate run lines #915 and source/drain regions, Fig.10, conductive structures contacting source and drain regions); a plurality of internal interconnect layers comprising metallization configured to connect the transistors to operate in parallel (Fig.3-11 conductive area to connect source are #1020/#1120/…#x20 and to connect drain are #1040/#1140/…#x40 ); a source electrode (#120) and a drain electrode (#130) for respectively connecting the sources and drains of the transistors to an external circuit (Fig.1-3); (See Vincairelli [col 3 line 53] – [col 5 line 18]) and
Vincairelli also teaches a bridging interconnect layer wherein a plurality of source bridging conductors that provide electrical connections for the sources of the transistors to the source electrode; and a plurality of drain bridging conductors that provide electrical connections for the drains of the transistors to the drain electrode. (under broadest reasonable interpretation, Vinciarelli’s plural source-side conductive paths such as #x20, constitute source bridging conductor providing electrical connections from the transistor sources to source electrode area #120. Vinciarelli’s plural drain-side conductive paths such as #x40, constitute drain bridging conductor providing electrical connections from the transistor sources to source electrode area #130. )
Vincairelli does not explicitly disclose the source and drain bridging conductors are undulating.
However, Stessin teaches in Fig.4 interconnect conductors (Fig.4 #140 & #116) in semiconductor devices that are intentionally formed with a wavy or undulating geometry, wherein the regions of the conductor are displace out of a nominal planar configurations (See Stessin Fig.2A, 2C, Fig,4 [0033 0035-0039, 0045] )
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Vincairelli’s semiconductor device with the teachings of Stessin, as identified above to have an undulating geometry interconnect conductor, in order to reduce inductance and the that smaller die-side bonds moderate the thermally induced bond stress. The modification would retain Vinciarelli’s internal low-resistance parallel metallization while predictably providing practical, low-inductance, thermally robust external source and drain connections.
Regarding Claim 2.
Vincairelli modified by Stessin teaches The electrical power switch according to claim 1
Stessin teaches wherein each of the undulating bridging conductors (#116 or #140) comprises at least one ripple in which a region of the bridging conductor is displaced perpendicular to a plane of the array of transistors. (See Stessin Fig.2A, 2C, Fig,4 [0033 0035-0039, 0045])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Vincairelli and Stessin with the teachings of Stessin, as identified above, in order to reduce inductance and the that smaller die-side bonds moderate the thermally induced bond stress. The modification would retain Vinciarelli’s internal low-resistance parallel metallization while predictably providing practical, low-inductance, thermally robust external source and drain connections.
Regarding Claim 4-6.
Vincairelli modified by Stessin teaches The electrical power switch according to claim 2
Stessin also teaches
(claim 4) wherein the at least one ripple has a harmonic-like shape.
(claim 5) wherein at least one of the bridging conductors has a ribbon shape.
(claim 6) wherein at least one of the bridging conductors has a wire shape. (See Stessin Fig.2A, 2C, Fig,4 [0033 0035-0039, 0045] )
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Vincairelli and Stessin with the teachings of Stessin, as identified above, in order to reduce inductance and the that smaller die-side bonds moderate the thermally induced bond stress. The modification would retain Vinciarelli’s internal low-resistance parallel metallization while predictably providing practical, low-inductance, thermally robust external source and drain connections.
Regarding Claim 7.
Vincairelli modified by Stessin teaches The electrical power switch according to claim 1
Vincairelli further teaches in Fig.9-10 wherein the plurality of interconnect layers comprises a first interconnect layer comprising a metallization layer that connects together the gates of all the transistors in the array of transistors. (Fig.9A/9B gate run line #915 and interconnect lines #910/#920)
Regarding Claim 8.
Vincairelli modified by Stessin teaches The electrical power switch according to claim 7
Vincairelli further teaches wherein the plurality of interconnect layers comprises a second interconnect layer comprising a first, source metallization region (#520) that connects together a plurality of the sources of the transistors, and a second, drain metallization region (#340) that connects together a plurality of the drains of the transistors. (Fig.3 #340 drain metallization region, Fig,5 #520 source metallization regions [col 5 line 66—col 8 line 14])
Regarding Claim 9.
Vincairelli modified by Stessin teaches The electrical power switch according to claim 8
Vincairelli further teaches wherein the source metallization region comprises a plurality of source tines (#620) each of which extends from a common source backbone (#520 conductive areas) and overlays a row of the transistors and electrically connects together the sources of a plurality of the transistors in the row. (Fig.5-6)
Regarding Claim 10.
Vincairelli modified by Stessin teaches The electrical power switch according to claim 8
Vincairelli further teaches wherein the drain metallization region comprises a plurality of drain tines (#640) each of which extends from a common drain backbone (#340/#540 conductive areas) and overlays a row of the transistors and electrically connects together the drains of a plurality of the transistors in the row. (Fig.3, 5-6)
Regarding Claim 11.
Vincairelli modified by Stessin teaches The electrical power switch according to claim 9
Vincairelli does not explicitly disclose wherein the tines are tapered. However, tapering of metallization fingers is a well-known layout technique in power devices to manage current density and electromigration. Since finger/tine metallization is taught in Claim 9-10, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to taper such structure as this is an obvious design optimization.
Regarding Claim 12.
Vincairelli modified by Stessin teaches The electrical power switch according to claim 8
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Vincairelli further teaches wherein the plurality of interconnect layers comprising a third, band interconnect layer comprising a plurality of source metallization bands (#720) interleaved with a plurality of drain metallization bands (#740). (Fig.7 [col 10 line 29 -52])
Regarding Claim 13-14
Vincairelli modified by Stessin teaches The electrical power switch according to claim 12,
Vincairelli further teaches
(claim 13) wherein each of the source metallization bands (#720) electrically connects together a plurality of the source tines in the second interconnect layer (#620).
(claim 14) wherein each of the drain metallization bands (#740) electrically connects together a plurality of the drain tines (#640) in the second interconnect layer. ([col 9 line 56] – [col 10 line 47] Fig.6-7A)
Regarding Claim 17.
Vincairelli modified by Stessin teaches The electrical power switch according to claim 1
Vincairelli further teaches wherein the transistors are lateral field effect (LFET) transistors. ([col 3 line 6-29] Fig.9A-10)
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Vinciarelli et. al (US-9269661-B1, hereinafter Vinciarelli), in view of Stessin et.al. (WO-2013/179205-A1, hereinafter Stessin), and further in view of Luechinger et.al. (US-20100214754-A1, hereinafter Luechinger)
Regarding Claim 15-16.
Vincairelli modified by Stessin teaches The electrical power switch according to claim 12
Luechinger teaches
(claim 15) wherein each of the plurality of undulating source bridging conductors connects together a plurality of the source bands in the third interconnect layer.
(claim 16) wherein each of the plurality of undulating drain bridging conductors connects together a plurality of the drain bands in the third interconnect layer. (Luechinger teaches a continuous conductive ribbon #404 having multiple stich bonds #500 at spaced locations along a semiconductor-die metallization. The ribbon forms loops between stitch areas, and the multiple stiches reduce spreading resistance and increase current flow to an external terminal, see [0042,0045] Fig. 4A-4B, Fig.11. Luechinger also demonstrates selective stich placement among intervening conductor features, see [0060-0061] Fig.10-Fig.11)
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Vincairelli and Stessin with the teachings of Luechinger, as identified above, in order to reduce spreading resistance and increase current capability while preserving electrical isolation. The resulting source bridging conductor would each connect a plurality of source bands, and the resulting drain bridging conductors would each connect a plurality of drain bands. As claimed.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein … the at least one ripple as a function of length along a source bridging conductor adjacent to a drain bridging conductor is out of phase with the at least one ripple as a function of length along the drain bridging conductor. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
McKnight-Macneil et. al. - US-2016/0268190-A1
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/SOPHIA W KAO/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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