DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/8/2024, 5/14/2025 and 10/8/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the claimed limitation “the bridging connectors”, as recited in claim 2, is unclear as to whether said limitation is the same as or different from the “bridging conductors”, as recited in claim 1. Therefore, it is indefinite. Claims 3-4 depend from claim 2 so they are rejected for the same reason.
For purposes of examination, “the bridging connectors” will be interpreted as “the bridging conductors.”
Regarding claim 3: the claim attempts to define a phase relationship between two components. However, the text compares the ripple on a “source bridging conductor” to the ripple on “the source bridging conductor” As it is written, the claim does not clearly identify the two structures or waveforms being compared. The claim appears to compares the components to itself (or ambiguously to a second, undefined source conductor). As a result, the scope of claim 3 is unclear and the claim cannot be meaningfully examined for compliance with the requirement of 35 U.S.C. 102 and 103. Accordingly, examination of claim 3 on the merits is deferred until the indefiniteness is resolved.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-17 are rejected under 35 U.S.C. 103 as being unpatentable over Vinciarelli et. al ( US-9269661-B1, hereinafter Vinciarelli), and further in view of Rogers et.al. (US-2008/0157235-A1, hereinafter “Rogers”
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Regarding Claim 1. An electrical power switch, the power switch comprising:
an array of rows and columns of transistors, each transistor having a source, drain, and gate (See Vinciarelli Fig,9A-9B, gate run lines #915 and source/drain regions, Fig.10, conductive structures contacting source and drain regions); a plurality of internal interconnect layers comprising metallization configured to connect the transistors to operate in parallel (Fig.3/Fig.5 conductive area and via #340/$540); a source electrode and a drain electrode for respectively connecting the sources and drains of the transistors to an external circuit (Fig.1-3); (See Vincairelli [col 1 line 14] – [col 2 line 29]) and
Vincairelli also teaches a bridging interconnect layer wherein a plurality of source bridging conductors that provide electrical connections for the sources of the transistors to the source electrode; and a plurality of drain bridging conductors that provide electrical connections for the drains of the transistors to the drain electrode. ([col 3 line 13-29])
Vincairelli does not explicitly disclose bridging conductors are undulating.
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However, Rogers teaches interconnect conductors in semiconductor devices that are intentionally formed with a wavy or undulating geometry, wherein the regions of the conductor are displace out of a nominal planar configurations (See Rogers Abstract., Fig, 2-5, 13-14)
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Vincairelli’s semiconductor device with the teachings of Rogers, as identified above to have an undulating geometry interconnect conductor, in order to improve the mechanical and electrical performance of the interconnect..
Regarding Claim 2.
Vincairelli modified by Rogers teaches The electrical power switch according to claim 1
Rogers also teaches in Fig. 14B wherein each undulating bridging connectors comprises at least one ripple in which a region of the bridging connector is displaced perpendicular to a plane of the array of transistors. (Rogers Fig.2 and Fig. 14 wavy/ripple shaped electrical interconnects/bridges)
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Vincairelli and Rogers with the teachings of Rogers, as identified above, in order to improve the mechanical robustness and compliance of semiconductor interconnects and to enhance the reliability of the interconnect.
Regarding Claim 4-6.
Vincairelli modified by Rogers teaches The electrical power switch according to claim 2
Rogers also teaches
(claim 4) wherein the at least one ripples has a harmonic-like shape. (Fig.2-5 smooth sin-wave shaped electrical interconnect)
(claim 5) wherein at least one of the bridging conductors has a ribbon shape.
(claim 6) wherein at least one of the bridging conductors has a wire shape. ([0015] The component itself may be of any shape, such as a membrane, wire, or a ribbon.)
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Vincairelli and Rogers with the teachings of Rogers, as identified above, in order to improve the mechanical robustness and compliance of semiconductor interconnects and to enhance the reliability of the interconnect.
Regarding Claim 7.
Vincairelli modified by Rogers teaches The electrical power switch according to claim 1
Vincairelli further teaches in Fig.9-10 wherein the plurality of interconnect layers comprises a first interconnect layer comprising a metallization layer that connects together the gates of all the transistors in the array of transistors. (Fig.9A/9B gate run line #915 and interconnect lines #910/#920)
Regarding Claim 8.
Vincairelli modified by Rogers teaches The electrical power switch according to claim 7
Vincairelli further teaches wherein the plurality of interconnect layers comprises a second interconnect layer comprising a first, source metallization region (#520) that connects together a plurality of the sources of the transistors, and a second, drain metallization region (#340) that connects together a plurality of the drains of the transistors. (Fig.3 #340 drain metallization region, Fig,5 #520 source metallization regions [col 5 line 66—col 8 line 14])
Regarding Claim 9.
Vincairelli modified by Rogers teaches The electrical power switch according to claim 8
Vincairelli further teaches wherein the source metallization region comprises a plurality of source tines (#620) each of which extends from a common source backbone (#520 conductive areas) and overlays a row of the transistors and electrically connects together the sources of a plurality of the transistors in the row. (Fig.5)
Regarding Claim 10.
Vincairelli modified by Rogers teaches The electrical power switch according to claim 8
Vincairelli further teaches wherein the drain metallization region comprises a plurality of drain tines (#640) each of which extends from a common drain backbone (#340 conductive areas) and overlays a row of the transistors and electrically connects together the drains of a plurality of the transistors in the row. (Fig.3)
Regarding Claim 11.
Vincairelli modified by Rogers teaches The electrical power switch according to claim 9
Vincairelli does not explicitly disclose wherein the tines are tapered. However, tapering of metallization fingers is a well-known layout technique in power devices to manage current density and electromigration. Since finger/tine metallization is taught in Claim 9-10, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to taper such structure as this is an obvious design optimization.
Regarding Claim 12.
Vincairelli modified by Rogers teaches The electrical power switch according to claim 8
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Vincairelli further teaches wherein the plurality of interconnect layers comprising a third, band interconnect layer comprising a plurality of source metallization bands (#720) interleaved with a plurality of drain metallization bands (#740). (Fig.7 [col 10 line 29 -52])
Regarding Claim 13-14
Vincairelli modified by Rogers teaches The electrical power switch according to claim 12,
Vincairelli further teaches
(claim 13) wherein each of the source metallization bands (#720) electrically connects together a plurality of the source tines in the second interconnect layer (#620).
(claim 14) wherein each of the drain metallization bands (#740) electrically connects together a plurality of the drain tines (#640) in the second interconnect layer. ([col 9 line 56] – [col 10 line 47])
Regarding Claim 15.
Vincairelli modified by Rogers teaches The electrical power switch according to claim 12
Vincairelli teaches wherein each of the plurality of source bridging conductors connects together a plurality of the source bands in the third interconnect layer. ([col 9 line 56] – [col 10 line 47])
Rogers also teaches using undulating interconnects to relieve thermal/mechanical stress. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use the undulating conductors of Rogers to form the final connection stage -- specifically, connecting the source bands to the source electrode, to prevent cracking between the dense band layer and to enhance the performance.
Regarding Claim 16.
Vincairelli modified by Rogers teaches The electrical power switch according to claim 12
Vincairelli teaches wherein each of the plurality of drain bridging conductors connects together a plurality of the drain bands in the third interconnect layer. ([col 9 line 56] – [col 10 line 47])
Rogers also teaches using undulating interconnects to relieve thermal/mechanical stress. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use the undulating conductors of Rogers to form the final connection stage -- specifically, connecting the drain bands to the drain electrode, to prevent cracking between the dense band layer and to enhance the performance.
Regarding Claim 17.
Vincairelli modified by Rogers teaches The electrical power switch according to claim 1
Vincairelli further teaches wherein the transistors are lateral field effect (LFET) transistors. ([col 3 line 6-29])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Heilbronner et. al. - US-20050024805-A1
Cottet et. al. - US-20170338162-A1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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/SOPHIA W KAO/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817