DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US Publication No. 2023/0307517) in view of Haeberlen et al (US Publication No. 2021/0134968).
Regarding claim 1, Watanabe discloses a semiconductor device, comprising: a semiconductor substrate Fig 1, 10 ¶0024; a transistor Fig 1, 100 formed on the semiconductor substrate Fig 1, 10 and including a source electrode Fig 1, 14, a drain electrode Fig 1, 18, and a gate electrode Fig 1, 36; a source pad Fig 1, 12 electrically connected to the source electrode Fig 1, 14; a drain pad Fig 1, 16 electrically connected to the drain electrode Fig 1, 18; a gate pad Fig 1, 34 connected to the gate electrode Fig 1, 36; a specified pad Fig 1, 20; and a capacitor Fig 6 ¶0046 including a source-side electrode Fig 6, electrically connected to the source electrode Fig 6, and a specified electrode ¶0031, electrically connected to the specified pad Fig 6, 20 and arranged facing the source-side electrode Fig 6.
Watanabe discloses all the limitations but silent on the arrangement of the insulation layer relative to the source/drain pad.
Whereas Haeberlen discloses a semiconductor device, comprising: a transistor ¶0050 including a source electrode Fig 2, 26, a drain electrode Fig 2, 27, and a gate electrode Fig 2, 28; an insulation layer Fig 3D-3F, 43 arranged on the semiconductor substrate Fig 3D-3F; a source pad Fig 3D-3F, 34 ¶0064 formed on a head surface of the insulation layer Fig 3D-3F and electrically connected to the source electrode Fig 3A and Fig 3F; a drain pad Fig 3D-3F, 35 ¶0064 formed on the head surface of the insulation layer and electrically connected to the drain electrode Fig 3A and Fig 3E; a gate pad Fig 3D-3F, 36 ¶0065 formed on the head surface of the insulation layer and connected to the gate electrode Fig 3A and Fig 3F; a specified pad formed on the head surface of the insulation layer Fig 3A -Fig 3F; and a capacitor Fig 3A -Fig 3F, 40 including a source-side electrode Fig 3A -Fig 3F, electrically connected to the source electrode Fig 3A -Fig 3F.
Watanabe and Haeberlen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Watanabe because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Watanabe and incorporate the teachings of Haeberlen to improve device isolation.
Regarding claim 2, Watanabe in view of Haeberlen discloses wherein: the specified electrode ¶0031 includes an opposing portion facing the source pad with part of the insulation layer located in between Fig 1 ¶0046-0047, 0059, 0061; and the source side electrode includes an opposed portion formed by the source pad where the source pad faces the opposing portion Fig 1.
Regarding claim 3, Watanabe in view of Haeberlen discloses wherein: the specified electrode further includes a connecting portion electrically connecting the opposing portion and the specified pad; and the specified electrode extends across both of the source pad and the specified pad in a view taken in a thickness direction of the semiconductor substrate ¶0031 and 0071 Fig 1.
Regarding claim 4, Watanabe in view of Haeberlen discloses a via extending through the insulation layer between the connecting portion and the specified pad and electrically connecting the connecting portion and the specified pad Fig 3 ¶0057-0059.
Claims 5-6, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US Publication No. 2023/0307517) in view of Haeberlen et al (US Publication No. 2021/0134968) and Noebauer et al (US Publication No. 2021/0351168).
Regarding claim 5, Watanabe discloses all the limitations but silent on the arrangement of the electrodes.
Whereas Noebauer discloses wherein the opposing portion is formed on a back surface of the insulation layer Fig 2, Fig 5B-5C, Fig 6B, Fig 7B.
Watanabe and Noebauer are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Watanabe because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Watanabe and incorporate the teachings of Noebauer to improve device connectivity.
Regarding claim 6, Noebauer discloses wherein the opposing portion is an embedded conductive layer embedded in the insulation layer Fig 2, Fig 5B-5C, Fig 6B, Fig 7B.
Regarding claim 13, Noebauer discloses wherein the specified pad is located closer to the source pad than the gate pad on the head surface of the insulation layer Fig 2, Fig 3B and Fig 4C.
Regarding claim 14, Noebauer discloses wherein the gate pad is located closer to the drain pad than the source pad on the head surface of the insulation layer ¶0072 Fig 4D.
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US Publication No. 2023/0307517) in view of Haeberlen et al (US Publication No. 2021/0134968) and Yamada (US Publication No. 2023/0170409).
Regarding claim 16, Watanabe discloses all the limitations but silent on the encapsulation resin. Whereas Yamada discloses an encapsulation resin Fig 14, 1231 encapsulating the semiconductor device ¶0076 Fig 14. Watanabe and Yamada are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Watanabe because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Watanabe and incorporate the teachings of Yamada to improve device isolation.
Regarding claim 17, Yamada discloses a specified wire connecting the specified pad and the gate pad Fig 14.
Regarding claim 18, Yamada discloses wherein the specified pad is electrically disconnected from the gate pad Fig 14.
Regarding claim 19, Yamada discloses a source lead, a drain lead, and a gate lead; a source wire connecting the source lead and the source pad; a drain wire connecting the drain lead and the drain pad; and a gate wire connecting the gate lead and the gate pad Fig 14.
Allowable Subject Matter
Claims 7-12, 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811