DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 02/20/2026 has been entered.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 02/20/2026, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with a new reference, US 20120193789 A1 to Hu, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,3,4,11, 13-14,16-17 and 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210098421 A1, of the record) in view of Chen et al. (US 20230163114 A1, hereinafter Chen, of the record) and further in view of Hu et al. (US 20120193789 A1, hereinafter Hu).
Re: Independent Claim 1, Wu discloses a semiconductor package comprising:
a front side redistribution layer (110 first redistribution structure in [0074], Fig. 7);
a three-dimensional integrated circuit (3D IC) structure (530 semiconductor die in [0077], Fig. 7) disposed on the front side redistribution layer (110 Fig. 7), the 3D IC structure (530 Fig. 7) including a first semiconductor chip die (530-1 wherein 530 is similar to 330 and 330 is similar to 130, then 530 comprise two dies 530-1 and 530-2 in [0033, 0099, 0105], Fig. 7) having through-silicon vias (TSVs) (534 TSVs in [0077], Fig. 7) and a second semiconductor chip die (530-2 wherein 530 comprise two dies 530-1 and 530-2 in [0033, 0099, 0105], Fig. 7);
a molding material (140 first insulating layer in [0076], Fig. 7) disposed on the front side redistribution layer (110 Fig. 7) to encapsulate the first semiconductor chip die (530-1 Fig. 7) and the second semiconductor chip die (530-2 Fig. 7); and
a back side redistribution layer (350 second redistribution structure in [0081], Fig. 7) disposed on the molding material (140 Fig. 7).
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Wu’s Figure 7-Annotated.
Wu does not expressly disclose a second semiconductor chip die disposed on the first semiconductor chip die wherein the second semiconductor chip die has a first surface facing the first semiconductor die and a second surface opposing the first surface and coupled to the front side redistribution layer by the TSVs; a plurality of connection members disposed between the first semiconductor chip die and the second semiconductor chip die; an insulating member disposed between the first semiconductor chip die and the second semiconductor chip die to surround the plurality of connection members; and a molding material to encapsulate the insulating member and covering the second surface of the second semiconductor chip die.
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Chen’s Figure 1-Annotated.
However, in the same semiconductor device field of endeavor, Chen discloses a second semiconductor chip die (Chen: 60 a second semiconductor chip in [0065], Fig. 1) disposed on the first semiconductor chip die (Chen:70 a first semiconductor chip in [0065], Fig. 1) wherein the second semiconductor chip die (Chen: 60) has a first surface facing the first semiconductor die (Chen: 70) and a second surface opposing (Fig. 1) the first surface; a plurality of connection members (Chen: 80 metal conductive layer in [0073], Fig. 1) disposed between the first semiconductor chip die (Chen: Fig.1, 70) and the second semiconductor chip die (Chen: Fig.1, 60); an insulating member (Chen: 90 first filler layer made of epoxy resin as a molded underfill (MUF) material in [0069], Fig. 1) disposed between the first semiconductor chip die (Chen: Fig.1, 70) and the second semiconductor chip die (Chen: Fig.1, 60) to surround the plurality of connection members (Chen: Fig.1, 80); and a molding material (Chen: 100 first encapsulating layer in [0069], Fig. 1) to encapsulate the insulating member (Chen: Fig.1, 90).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chen’s feature of a second semiconductor chip die disposed on the first semiconductor chip die; a plurality of connection members disposed between the first semiconductor chip die and the second semiconductor chip die; an insulating member disposed between the first semiconductor chip die and the second semiconductor chip die to surround the plurality of connection members; and a molding material to encapsulate the insulating member to Wu’s device to have the second semiconductor chip die coupled to the front side redistribution layer by the TSVs to reduce the minimum line width/line spacing of the package ([0064], Chen).
Wu modified by Chen does not expressly disclose a molding material covering the second surface of the second semiconductor chip die.
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Hu’s Figure 2G-Annotated.
However, in the same semiconductor device field of endeavor, Hu discloses a molding material (23, [0042], Fig. 2G) covering the second surface of the semiconductor chip die (20, [0043], Fig. 2G).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Wu’s molding material covering the second surface of the second semiconductor chip die according to Hu’s molding material to encapsulant the electronic element and for filling the gap between the first and second substrates ([0041], Hu).
Re: Claim 3, Wu modified by Chen and Hu discloses the semiconductor package of claim 1, semiconductor package of claim 1, wherein: the insulating member (90, Fig.1 Chen) includes a molded underfill (MUF) material ([0069], Chen).
Re: Claim 4, Wu modified by Chen and Hu discloses the semiconductor package of claim 1, wherein: the insulating member (90, Fig.1 Chen) includes a non-conductive film (NCF) (an epoxy resin in [0069], Chen).
Re: Independent Claim 11, Wu discloses a semiconductor package comprising:
a front side redistribution layer (110 first redistribution structure in [0074], Fig. 7);
a three-dimensional integrated circuit (3D IC) structure (530 semiconductor die in [0077], Fig. 7) disposed on the front side redistribution layer (110), the 3D IC structure (530) including a first semiconductor chip die (530-1 wherein 530 is similar to 330 and 330 is similar to 130, then 530 comprise two dies 530-1 and 530-2 in [0033, 0099, 0105], Fig. 7) having through-silicon vias (TSVs) (534 TSVs in [0077], Fig. 7) and a second semiconductor chip die (530-2 wherein 530 comprise two dies 530-1 and 530-2 in [0033, 0099, 0105], Fig. 7);
a plurality of second connection members (436,438,112 conductive pads 436, conductive bumps 438 and conductive layer 112 in [0064, 0065], Figs. 6A, 7) disposed between the first semiconductor chip die (530-1 Fig. 7) and the front side redistribution layer (110 Fig. 7) to electrically couple the first semiconductor chip die (530-1 Fig. 7) to the front side redistribution layer (110 Fig. 7);
a plurality of conductive posts (120 TIVs in [0074], Fig. 7) bonded to the front side redistribution layer (110 Fig. 7) and disposed side by side next to the 3D IC structure (530 Fig. 7) on the front side redistribution layer (110 Fig. 7);
a molding material (140 first insulating layer in [0076], Fig. 7) disposed on the front side redistribution layer (110 Fig. 7) to encapsulate the first semiconductor chip die (530-1 Fig. 7), the second semiconductor chip die (530-2 Fig. 7), the plurality of second connection members (436,438,112 Figs. 6A, 7), and the plurality of conductive posts (120 Fig. 7);
a back side redistribution layer (350 second redistribution structure in [0081], Fig. 7) disposed on the molding material (140 Fig. 7) and the plurality of conductive posts (120 Fig. 7) and bonded to the plurality of conductive posts (120 Fig. 7); and
a third semiconductor chip die (200A device package in [0070], Fig. 7) disposed on the back side redistribution layer (350 Fig. 7).
Wu does not expressly disclose a second semiconductor chip die disposed on the first semiconductor chip die, wherein the second semiconductor chip die has a first surface facing the first semiconductor die and a second surface opposing the first surface and coupled to the front side redistribution layer by the through-silicon vias (TSVs); a plurality of first connection members disposed between the first semiconductor chip die and the second semiconductor chip die to electrically couple the first semiconductor chip die to the second semiconductor chip die; an insulating member disposed between the first semiconductor chip die and the second semiconductor chip die to surround the plurality of first connection members; and a molding material to encapsulate the insulating member, and covering the second surface of the second semiconductor chip die.
However, in the same semiconductor device field of endeavor, Chen discloses a second semiconductor chip die (Chen: 60 a second semiconductor chip in [0065], Fig. 1) disposed on the first semiconductor chip die (Chen: 70 a first semiconductor chip in [0065], Fig. 1), wherein the second semiconductor chip die (Chen: 60) has a first surface facing the first semiconductor die (Chen: 70) and a second surface opposing (Fig. 1) the first surface; a plurality of first connection members (Chen: 80 metal conductive layer in [0073], Fig. 1) disposed between the first semiconductor chip die (Chen: Fig.1 70) and the second semiconductor chip die (Chen: Fig.1, 60) to electrically couple the first semiconductor chip die (Chen: Fig.1, 70) to the second semiconductor chip die (Chen: Fig.1, 60); an insulating member (90 first filler layer made of epoxy resin in [0069], Fig. 1) disposed between the first semiconductor chip die (Chen: Fig.1, 70) and the second semiconductor chip die (Chen: Fig.1, 60) to surround the plurality of first connection members (Chen: Fig.1, 80); and a molding material (Chen: 100 first encapsulating layer in [0069], Fig. 1) to encapsulate the insulating member (Chen: Fig.1, 90).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chen’s feature of a second semiconductor chip die disposed on the first semiconductor chip die; a plurality of first connection members disposed between the first semiconductor chip die and the second semiconductor chip die to electrically couple the first semiconductor chip die to the second semiconductor chip die; an insulating member disposed between the first semiconductor chip die and the second semiconductor chip die to surround the plurality of first connection members; and a molding material to encapsulate the insulating member to Wu’s device to have the second semiconductor chip die coupled to the front side redistribution layer by the through-silicon vias (TSVs) to reduce the minimum line width/line spacing of the package ([0064], Chen).
Wu modified by Chen does not expressly disclose a molding material covering the second surface of the second semiconductor chip die.
However, in the same semiconductor device field of endeavor, Hu discloses a molding material (23, [0042], Fig. 2G) covering the second surface of the semiconductor chip die (20, [0043], Fig. 2G).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Wu’s molding material covering the second surface of the second semiconductor chip die according to Hu’s molding material to encapsulant the electronic element and for filling the gap between the first and second substrates ([0041], Hu).
Re: Claim 13, Wu modified by Chen and Hu discloses the semiconductor package of claim 11, wherein: the second semiconductor chip die (530-2, Fig. 7 Wu) includes a communication chip or a sensor (a sensor in [0030], Wu).
Re: Claim 14, Wu modified by Chen and Hu discloses the semiconductor package of claim 11,
Wu modified by Chen does not expressly disclose wherein: the third semiconductor chip die includes a semiconductor memory.
However, in the same semiconductor device field of endeavor, Wu discloses
in other embodiment, wherein: the third semiconductor chip die (Wu: 200A including 202, in [0021], Fig. Fig. 1E) includes a semiconductor memory (in [0038], Fig. 1E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Wu’s feature wherein: the third semiconductor chip die includes a semiconductor memory to the combination of the Wu, Chen and Hu to perform various functions ([0038], Wu).
Re: Claim 16, Wu modified by Chen and Hu discloses the semiconductor package of claim 11, wherein: the molding material (140, Fig. 7 Wu) includes an epoxy molding compound (EMC) (epoxy mold compound in [0067], Wu).
Re: Independent Claim 17, Wu discloses a method of fabricating a semiconductor package comprising:
forming a front side redistribution layer (110 first redistribution structure in [0074], Fig. 7) on a carrier (TC temporary carrier in [0020], Figs. 6A-C);
forming a three-dimensional integrated circuit (3D IC) structure (530 semiconductor die in [0077], Fig. 7) on the front side redistribution layer (110 Fig. 7), wherein the forming of the 3D IC structure comprises: mounting a first semiconductor chip die (530-1 wherein 530 is similar to 330 and 330 is similar to 130, then 530 comprise two dies 530-1 and 530-2 in [0033, 0099, 0105], Fig. 7) to the front side redistribution layer (110 Fig. 7); and
forming a molding material to encapsulate the first semiconductor chip die (530-1 Fig. 7) on the front side redistribution layer (110 Fig. 7) within a molding material (140 first insulating layer in [0076], Figs. 6A-C, 7); and
forming a back side redistribution layer (350 second redistribution structure in [0081], Fig. 7) on the molding material (140 Fig. 7).
Wu does not expressly disclose bonding a second semiconductor chip die to the first semiconductor chip die using a plurality of connection members, wherein the plurality of connection members are surrounded by an insulating member and the second semiconductor chip die has a first surface facing the first semiconductor die and a second surface opposing the first surface; forming a molding material to encapsulate the second semiconductor chip die, and the insulating member on the front side redistribution layer and to cover the second surface of the second semiconductor hip die.
However, in the same manufacturing of a semiconductor device field of endeavor, Chen discloses bonding a second semiconductor chip die (Chen:60 a second semiconductor chip in [0065], Fig. 1) to the first semiconductor chip die (Chen:70 a first semiconductor chip in [0065], Fig. 1) using a plurality of connection members (Chen: 80 metal conductive layer in [0073], Fig. 1), wherein the plurality of connection members (Chen: Fig.1 80) are surrounded by an insulating member (Chen:90 first filler layer made of epoxy resin in [0069], Fig. 1) and the second semiconductor chip die (Chen: 60) has a first surface facing the first semiconductor die (Chen: 70) and a second surface opposing (Fig. 1) the first surface; forming a molding material (Chen:100 first encapsulating layer in [0069], Fig. 1) to encapsulate the second semiconductor chip die (Chen: Fig.1 60), and the insulating member (Chen: Fig.1 90) on the front side redistribution layer (Chen:110 first rewiring layer in [0065], Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chen’s feature of bonding a second semiconductor chip die to the first semiconductor chip die using a plurality of connection members, wherein the plurality of connection members are surrounded by an insulating member; forming a molding material to encapsulate the second semiconductor chip die, and the insulating member on the front side redistribution layer to Wu’s method to reduce the minimum line width/line spacing of the package ([0064], Chen).
Wu modified by Chen does not expressly disclose forming a molding material to cover the second surface of the second semiconductor chip die.
However, in the same manufacturing of a semiconductor device field of endeavor, Hu discloses forming a molding material (23, [0042], Fig. 2G) to cover the second surface of the semiconductor chip die (20, [0043], Fig. 2G).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Wu’s molding material covering the second surface of the second semiconductor chip die according to Hu’s molding material to encapsulant the electronic element and for filling the gap between the first and second substrates ([0041], Hu).
Re: Claim 20, Wu modified by Chen and Hu discloses the method for fabricating the semiconductor package according to claim 17,
Wu modified by Chen and Hu does not expressly disclose further comprising: filling a molded underfill (MUF) material between the first semiconductor chip die and the second semiconductor chip die, after the bonding of the second semiconductor chip die to the first semiconductor chip die using the plurality of connection members.
However, in the same manufacturing of semiconductor device field of endeavor, Chen discloses further comprising: filling a molded underfill (MUF) material (Chen:90 first filler layer made of epoxy resin as a molded underfill material in [0069], Fig. 1) between (Figs. 8-9) the first semiconductor chip die (Chen:70 a first semiconductor chip in [0065], Fig. 1) and the second semiconductor chip die (Chen:60 a second semiconductor chip in [0065], Fig. 1), after the bonding of the second semiconductor chip die (Chen: Fig.1 60) to the first semiconductor chip die (Chen: Fig.1 70) using the plurality of connection members (Chen:80 metal conductive layer in [0073], Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chen’s method of filling a molded underfill (MUF) material between the first semiconductor chip die and the second semiconductor chip die, after the bonding of the second semiconductor chip die to the first semiconductor chip die using the plurality of connection members to the combination of the Wu, Chen and Hu to reduce the minimum line width/line spacing of the package ([0064], Chen).
Claim(s) 2 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wu in view of Chen, in view of Hu and further in view of Liu et al. (US 20240047332 A1, hereinafter Liu, of the record).
Re: Claim 2, Wu modified by Chen and Hu discloses the semiconductor package of claim 1,
Wu modified by Chen and Hu does not expressly disclose wherein: each connection member of the plurality of connection members includes a micro bump.
However, in the same semiconductor device field of endeavor, Liu discloses
wherein: each connection member (Liu:121’ second die connectors in [0022] Fig. 1A) of the plurality of connection members (Liu: plurality of 121′, Fig. 1A) includes a micro bump (micro-bumps in [0022]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Liu’s feature wherein: each connection member of the plurality of connection members includes a micro bump to the combination of the Wu, Chen and Hu to tune the design requirements ([0022], Liu).
Claim(s) 5-10 and 18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wu in view of Chen, in view of Hu and further in view of Yu et al. (US 20220077117 A1, hereinafter Yu, of the record).
Re: Claim 5, Wu modified by Chen and Hu discloses the semiconductor package of claim 1,
Wu modified by Chen and Hu does not expressly disclose wherein: each connection member of the plurality of connection members includes a first bonding pad bonded to the first semiconductor chip die, and a second bonding pad bonded to the second semiconductor chip die.
However, in the same semiconductor device field of endeavor, Yu discloses wherein: each connection member (Yu:142-242 bond pads 142 and 242 in [0021], Fig. 3) of the plurality of connection members (Yu: plurality of 142-242 Fig. 3) includes a first bonding pad (Yu:242 bond pad in [0021], Fig. 3) bonded to the first semiconductor chip die (Yu:210’ device die in [0038], Fig. 14), and a second bonding pad (Yu:142 bond pad in [0021], Fig. 3) bonded to the second semiconductor chip die (Yu:110’ device die in [0020], Fig. 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yu’s feature wherein: each connection member of the plurality of connection members includes a first bonding pad bonded to the first semiconductor chip die, and a second bonding pad bonded to the second semiconductor chip die to the combination of the Wu, Chen and Hu to improve the electrical connections using a hybrid bonding ([0022], Yu).
Re: Claim 6, Wu modified by Chen, Hu and Yu discloses the semiconductor package of claim 5, wherein: the first bonding pad (242 Fig. 3 Yu) is directly bonded (Fig. 3, 14, Yu) to the second bonding pad (142 Fig. 3 Yu).
Re: Claim 7, Wu modified by Chen, Hu and Yu discloses the semiconductor package of claim 5, wherein: the first bonding pad (242 Fig. 3 Yu) and the second bonding pad (142 Yu) include copper (Cu) (copper-to-copper direct bonding [0021], Yu).
Re: Claim 8, Wu modified by Chen and Hu discloses the semiconductor package of claim 1,
Wu modified by Chen and Hu does not expressly disclose wherein: the insulating member includes a first insulating layer bonded to the first semiconductor chip die, and a second insulating layer bonded to the second semiconductor chip die.
However, in the same semiconductor device field of endeavor, Yu discloses
wherein: the insulating member (Yu:234-134 dielectric layers directly bonded in [0021], Figs. 3, 14) includes a first insulating layer (Yu:234 dielectric layer in [0021], Figs. 3, 14) bonded to the first semiconductor chip die (Yu:210’ device die in [0038], Fig. 14), and a second insulating layer (Yu:134 dielectric layer in [0021], Figs. 3, 14) bonded to the second semiconductor chip die (Yu:110’ device die in [0020], Fig. 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yu’s feature wherein: the insulating member includes a first insulating layer bonded to the first semiconductor chip die, and a second insulating layer bonded to the second semiconductor chip die to the combination of the Wu, Chen and Hu to improve the electrical connections using a hybrid bonding ([0022], Yu).
Re: Claim 9, Wu modified by Chen, Hu and Yu discloses the semiconductor package of claim 8, wherein: the first insulating layer (234, Figs. 3, 14 Yu) is directly bonded (Figs. 3, 14) to the second insulating layer (134, Figs. 3, 14 Yu).
Re: Claim 10, Wu modified by Chen, Hu and Yu discloses the semiconductor package of claim 8, wherein: the first insulating layer (234, Figs. 3, 14 Yu) and the second insulating layer (134, Figs. 3, 14 Yu) include silicon oxide ([0021], Yu).
Re: Claim 18, Wu modified by Chen and Hu discloses the method for fabricating the semiconductor package according to claim 17,
Wu modified by Chen and Hu does not expressly disclose wherein the bonding of the second semiconductor chip die to the first semiconductor chip die using the plurality of connection members is performed by hybrid bonding.
However, in the same manufacturing of a semiconductor device field of endeavor, Yu discloses wherein the bonding of the second semiconductor chip die (Yu:110’ device die in [0020], Fig. 14) to the first semiconductor chip die (Yu:210’ device die in [0038], Fig. 14) using the plurality of connection members (Yu:142-242 bond pads 142 and 242 in [0021], Fig. 3) is performed by hybrid bonding (Yu: [0021], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yu’s method wherein the bonding of the second semiconductor chip die to the first semiconductor chip die using the plurality of connection members is performed by hybrid bonding to the combination of the Wu, Chen and Hu to improve the electrical connections using a hybrid bonding ([0022], Yu).
Claim(s) 12 and 15 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wu in view of Chen, in view of Hu and further in view of Lin et al. (US 20160079220 A1, hereinafter Lin, of the record).
Re: Claim 12, Wu modified by Chen and Hu discloses the semiconductor package of claim 11,
Wu modified by Chen and Hu does not expressly disclose wherein: the first semiconductor chip die includes a central processing unit (CPU) or a graphic processing unit (GPU).
However, in the same semiconductor device field of endeavor, Lin discloses wherein: the first semiconductor chip die (Lin:302 system on chip (SOC) die in [0019], Fig. 1) includes a central processing unit (CPU) or a graphic processing unit (GPU) (a central processing unit (CPU) or a graphic processing unit (GPU) in [0019]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lin’s feature wherein: the first semiconductor chip die includes a central processing unit (CPU) or a graphic processing unit (GPU) to the combination of the Wu, Chen and Hu to improve the coupling effect ([0006], Lin).
Re: Claim 15, Wu modified by Chen and Hu discloses the semiconductor package of claim 11,
Wu modified by Chen and Hu does not expressly disclose wherein: the 3D IC structure includes a system-on-chip (SOC).
However, in the same semiconductor device field of endeavor, Lin discloses wherein: the 3D IC structure (302 is a system on chip (SOC) die in [0019], Fig. 1) includes a system-on-chip (SOC).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lin’s feature wherein: the 3D IC structure includes a system-on-chip (SOC) to the combination of the Wu, Chen and Hu to improve the coupling effect ([0006], Lin).
Claim(s) 19 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wu in view of Chen, in view of Hu and further in view of Lim (US 20230027248 A1, hereinafter Lim, of the record).
Re: Claim 19, Wu modified by Chen and Hu discloses the method for fabricating the semiconductor package according to claim 17, wherein the bonding of the second semiconductor chip die (Chen: Fig.1 60) to the first semiconductor chip die (Chen: Fig.1 70) using the plurality of connection members (Chen: Fig.1 80).
Wu modified by Chen and Hu does not expressly disclose wherein the bonding of the second semiconductor chip die to the first semiconductor chip die using the plurality of connection members comprises: attaching a non-conductive film (NCF) to the first semiconductor chip die; and attaching the second semiconductor chip die to the non-conductive film (NCF).
However, in the same manufacturing of semiconductor device field of endeavor, Lim discloses wherein the bonding of the second semiconductor chip die (Lim:804 second semiconductor die in [0020], Fig. 8) to the first semiconductor chip die (Lim:802 first semiconductor die in [0020], Fig. 8) comprises: attaching a non-conductive film (NCF) (Lim:806 non-conductive film in [0020], Fig. 8) to the first semiconductor chip die (Lim: Fig. 8 802); and attaching (Lim:804 is affixed to 802 by way of a non-conductive film 806 in [0020]) the second semiconductor chip die (Lim: Fig. 8 804) to the non-conductive film (NCF) (Lim: Fig. 8 806).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lim’s method wherein the bonding of the second semiconductor chip die to the first semiconductor chip die comprises: attaching a non-conductive film (NCF) to the first semiconductor chip die; and attaching the second semiconductor chip die to the non-conductive film (NCF) to the combination of the Wu, Chen and Hu to have wherein the bonding of the second semiconductor chip die to the first semiconductor chip die using the plurality of connection members comprises: attaching a non-conductive film (NCF) to the first semiconductor chip die; and attaching the second semiconductor chip die to the non-conductive film (NCF) to seek ways to improve performance and reliability in these semiconductor devices while keeping product costs in focus ([0002], Lim).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Che (US 20240145457 A1) teaches “FAN-OUT PACKAGING FOR A MULTICHIP PACKAGE”. This document is related to a semiconductor structure with a semiconductor device assembly may include a controller, a first mold compound surrounding the controller, a plurality of semiconductor dies, a second mold compound surrounding the plurality of semiconductor dies, and one or more through-mold interconnects electrically coupling the controller to the plurality of semiconductor dies.
Tsai et al. (US 20230065941 A1) teaches “SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME”. This document is related to a semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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