Prosecution Insights
Last updated: April 19, 2026
Application No. 18/457,528

PROCESSING METHOD OF WAFER

Non-Final OA §102
Filed
Aug 29, 2023
Examiner
CHIU, TSZ K
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Disco Corporation
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
3y 6m
To Grant
90%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
528 granted / 668 resolved
+11.0% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
29 currently pending
Career history
697
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
47.7%
+7.7% vs TC avg
§102
35.9%
-4.1% vs TC avg
§112
9.8%
-30.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 668 resolved cases

Office Action

§102
DETAILED ACTION General Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). Status of claim(s) to be treated in this office action: Independent: 1. Pending: 1-3. Specification The disclosure is objected to because of the following informalities: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: WAFER PROCESSING METHOD USING LASER-INDUCED MODIFIED LAYERS AND WATER-SOLUBLE RESIN. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Yoshikawa et al., US PG pub. 20060197260 A1. Re: Independent Claim 1, Yoshikawa discloses A processing method of a wafer (10, fig. 1-7) with a plurality of devices formed on a front surface (10a, fig. 3) thereof and defined by a plurality of intersecting dividing lines (103, fig. 3), the processing method comprising: a protective tape (12, fig. 3) arrangement step of arranging a protective tape (12, fig. 3) on the front surface (10a, fig. 3) of the wafer (10, fig. 1-7); a holding step of holding, on a chuck table, the wafer (10, fig. 1-7) on a side of the protective tape (12, fig. 3); a grinding step (fig. 4) of grinding the wafer (10, fig. 1-7) at a back surface thereof to thin the wafer (10, fig. 1-7); a protective tape (12, fig. 3) separation step of separating the protective tape (12, fig. 3) from the front surface (10a, fig. 3) of the wafer (10, fig. 1-7); a water-soluble resin (¶0046; for example acrylic resin can be water based or solvent based) application step of applying a water-soluble resin (¶0046; for example acrylic resin can be water based or solvent based) to the front surface (10a, fig. 3) of the wafer (10, fig. 1-7); a modified-layer (fig. 12-fig. 13) forming step of applying a laser beam (¶0051,¶0058-¶0062; fig. 8) of a wavelength that has transmissivity for the wafer (10, fig. 1-7), from the back surface of the wafer (10, fig. 1-7) with a focal point of the laser beam (¶0051,¶0058-¶0062; fig. 8) positioned corresponding to each of the dividing lines (103, fig. 3) inside the wafer (10, fig. 1-7), thereby forming modified-layers along the each of the dividing lines (103, fig. 3); a frame supporting step (354, fig. 10) of bonding a dicing tape (16, fig. 6) to a back surface of an annular frame (15, fig. 7) that centrally has an opening of an inner diameter greater than a diameter of the wafer (10, fig. 1-7), such that the dicing tape (16, fig. 6) closes the opening, and then disposing the wafer (10, fig. 1-7) in the opening with the back surface of the wafer (10, fig. 1-7) directed downwards, to bond the back surface of the wafer (10, fig. 1-7) to the dicing tape (16, fig. 6), thereby supporting the wafer (10, fig. 1-7) on the annular frame (15, fig. 7) via the dicing tape (16, fig. 6); a resin removing step (fig. 14;¶0003; adhesive film for die bonding called "die attach film" having a thickness of 20 to 40 .mu.m and made of a polyimide-based resin, epoxy-based resin or acrylic resin) of removing the wafer (10, fig. 1-7)-soluble resin from the front surface (10a, fig. 3) of the wafer (10, fig. 1-7); a dividing step (¶0063) of applying an external force (for example the holding arm 356 can apply external force to hold down the tape and wafer) to the wafer (10, fig. 1-7), thereby dividing the wafer (10, fig. 1-7) into individual device chips; and a pickup step (fig. 15) of picking up the device chips from the dicing tape (16, fig. 6). Re: Claim 2, Yoshikawa disclose(s) all the limitations of claim 1 on which this claim depends. Yoshikawa further discloses: wherein the water-soluble resin (¶0046; for example acrylic resin can be water based or solvent based) application step is performed before the protective tape (12, fig. 3) arrangement step, and the water-soluble resin (¶0046; for example acrylic resin can be water based or solvent based) is exposed in the protective tape (12, fig. 3) separation step. Re: Claim 3, Yoshikawa disclose(s) all the limitations of claim 1 on which this claim depends. Yoshikawa further discloses: wherein the frame supporting step (354, fig. 10) is performed before the modified-layer forming step (fig. 12 and fig. 13), and the laser beam (¶0051,¶0058-¶0062; fig. 8) is applied from a side (as shown the 522 is form a side) of the dicing tape (16, fig. 6) in the modified-layer forming step. Prior art made of record and not relied upon are considered pertinent to current application disclosure. * (“Nagai et al., US PG pub. 20060084239 A1”) Discloses a method of dividing a wafer having a plurality of dividing lines formed in a lattice pattern on the front surface, into individual chips along the dividing lines, the method comprising: a deteriorated layer forming step for forming a deteriorated layer in the inside of the wafer by applying a laser beam capable of passing through the wafer along the dividing lines; a wafer supporting step for putting one surface side of the wafer on a support tape which is mounted on an annular frame and shrinks by an external stimulus; a wafer-dividing step for dividing the wafer along the dividing lines where the deteriorated layer has been formed by exerting external force to the wafer which has been put on the support tape; and a chip spacing formation step for shrinking the shrink area between the inner periphery of the annular frame and the area, to which the wafer is affixed, in the support tape affixed to the divided wafer, by exerting an external stimulus to the shrink area. * (“Nakamura US PG pub. 20090124063 A1”) discloses a method of manufacturing a semiconductor device by which a wafer with devices formed in a plurality of regions demarcated by a plurality of streets formed in a grid pattern in the face-side surface of the wafer is divided along the streets into individual devices, and an adhesive film for die bonding is attached to the back-side surface of each of the devices. The adhesive film is attached to the back-side surface of the wafer divided into individual devices by exposing cut grooves formed along the streets by a dicing-before-grinding method, and thereafter the adhesive film is irradiated with a laser beam along the cut grooves through the cut grooves from the side of a protective tape adhered to the face-side surface of the wafer, so as to fusion-cut the adhesive film along the cut grooves. * (“Choo US patent 6723952 B2”) discloses a laser cutter for cutting an object being cut such as a two glasses-attached panel for LCD using a laser beam. The laser cutter includes a laser unit for irradiating a laser beam with a specific wavelength along a marked cutting line of the object, a pre-scriber for forming a pre-cut groove at starting edge of the marked cutting line, and a cooling unit for cooling the cutting line which said laser beam has been irradiated. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ajay Ojha can be reached on 571-272-8936. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Aug 29, 2023
Application Filed
Dec 28, 2025
Non-Final Rejection — §102
Apr 07, 2026
Interview Requested
Apr 14, 2026
Examiner Interview Summary
Apr 14, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
90%
With Interview (+10.5%)
3y 6m
Median Time to Grant
Low
PTA Risk
Based on 668 resolved cases by this examiner. Grant probability derived from career allow rate.

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