Prosecution Insights
Last updated: May 29, 2026
Application No. 18/457,528

PROCESSING METHOD OF WAFER

Non-Final OA §102
Filed
Aug 29, 2023
Priority
Sep 21, 2022 — JP 2022-150230
Examiner
CHIU, TSZ K
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Disco Corporation
OA Round
2 (Non-Final)
79%
Grant Probability
Favorable
2-3
OA Rounds
7m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
533 granted / 673 resolved
+11.2% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
27 currently pending
Career history
701
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
69.4%
+29.4% vs TC avg
§102
21.5%
-18.5% vs TC avg
§112
2.2%
-37.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 673 resolved cases

Office Action

§102
DETAILED ACTION General Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). Status of claim(s) to be treated in this office action: Independent: 1. Pending: 1-6. Newly added: 4-6. Information Disclosure Statement Applicant’s IDS(s) submitted on 2/20/2026 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record. Claim Objections Claim 1 objected to because of the following informalities: Claim 1 line 24, minor informalities “wafer-soluble resin” should be “water-soluble resin” Appropriate correction is required. Response to Arguments Applicant' s arguments with respect to claim(s) 1-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Nakamura US PG pub. 20170162521 A1. Re: Independent Claim 1, Nakamura discloses a protective tape (3, fig. 2A) arrangement step of arranging a protective tape (3, fig. 2A) on the front surface of the wafer (2, fig. 1-13); a holding step (fig. 3A) of holding on a chuck table (41, fig. 3A), the wafer (2, fig. 1-13) on a side of the protective tape (3, fig. 2A); a grinding step of grinding the wafer (2, fig. 1-13) at a back surface thereof to thin the wafer (2, fig. 1-13); a protective tape (3, fig. 2A) separation step of separating the protective tape (3, fig. 2A) from the front surface of the wafer (2, fig. 1-13); a water-soluble resin (60, fig. 7A) application step of applying a water-soluble resin (60, fig. 7A) to the front surface of the wafer (2, fig. 1-13) in liquid form via a water-soluble resin (60, fig. 7A) supply nozzle (621, fig. 7A); a modified-layer forming step (fig. 8-fig. 9) of applying a laser beam (¶0038) of a wavelength that has transmissivity for the wafer (2, fig. 1-13), from the back surface of the wafer (2, fig. 1-13) with a focal point of the laser beam (¶0038) positioned corresponding to each of the dividing lines (26, fig. 9c) inside the wafer (2, fig. 1-13), thereby forming modified layers (25, fig. 9c) along the each of the dividing lines (26, fig. 9c); a frame supporting step (¶0054) of bonding a dicing tape (T, fig. 8) to a back surface of an annular frame (F, fig. 6) that centrally has an opening of an inner diameter greater than a diameter of the wafer (2, fig. 1-13), such that the dicing tape (T, fig. 8) closes the opening, and then disposing the wafer (2, fig. 1-13) in the opening with the back surface of the wafer (2, fig. 1-13) directed downwards, to bond the back surface of the wafer (2, fig. 1-13) to the dicing tape (T, fig. 8), thereby supporting the wafer (2, fig. 1-13) on the annular frame (F, fig. 6) via the dicing tape (T, fig. 8); a resin removing step (fig. 14A) of removing the wafer-soluble resin from the front surface of the wafer (2, fig. 1-13) by supplying water to the water-soluble resin (60, fig. 7A); a dividing step (fig. 15) of applying an external force (¶0069) to the wafer (2, fig. 1-13), thereby dividing the wafer (2, fig. 1-13) into individual device chips; and a pickup step (¶0077) of picking up the device chips from the dicing tape (T, fig. 8). Re: Claim 2, Nakamura disclose(s) all the limitations of claim 1 on which this claim depends. Nakamura further discloses: wherein the water-soluble resin (60, fig. 7A) application step is performed before the protective tape (3, fig. 2A) arrangement step, and the water-soluble resin (60, fig. 7A) is exposed in the protective tape (3, fig. 2A) separation step. Re: Claim 3, Nakamura disclose(s) all the limitations of claim 1 on which this claim depends. Nakamura further discloses: wherein the frame supporting step (¶0054) is performed before the modified-layer forming step (fig. 8-fig. 9), and the laser beam (¶0038) is applied from a side of the dicing tape (T, fig. 8) in the modified-layer forming step (fig. 8-fig. 9). Re: Claim 4, Nakamura disclose(s) all the limitations of claim 1 on which this claim depends. Nakamura further discloses: wherein the water-soluble resin (60, fig. 7A) supply nozzle (621, fig. 7A) is disposed above the chuck table (41, fig. 3A). Re: Claim 5, Nakamura disclose(s) all the limitations of claim 1 on which this claim depends. Nakamura further discloses: wherein, in the resin removing step (fig. 14A), the water is supplied to the water-soluble resin (60, fig. 7A) by a disk-shaped shower unit (92, fig. 14A) disposed above the chuck table (41, fig. 3A). Re: Claim 6, Nakamura disclose(s) all the limitations of claim 1 on which this claim depends. Nakamura further discloses: wherein the water-soluble resin (60, fig. 7A) application step is performed before the modified-layer forming step (fig. 8-fig. 9). Prior art made of record and not relied upon are considered pertinent to current application disclosure. * (“Nakamura US PG pub. 20160365270 A1”) Discloses a method of processing a wafer includes coating the front side of the wafer with a water-soluble liquid resin to form a thin film; fixing the wafer to a protective plate for protecting the front side of the wafer, with a bond material interposed between the protective plate and the thin film; holding by a chuck table the protective plate with the wafer fixed thereto and grinding the back side of the wafer to make the wafer have a predetermined thickness; releasing step of releasing the bond material together with the protective plate to which the wafer has been fixed; and supplying water to the bond material remaining on the front side of the wafer to remove the thin film together with the bond material. * (“Sugiya US PG pub. 20200111658 A1”) discloses a wafer processing method includes: a bonding step of bonding a front surface side of a first wafer chamfered at a peripheral edge portion thereof to a front surface side of a second wafer; a grinding step of holding a back surface side of the second wafer by a chuck table and grinding a back surface of the first wafer to thin the first wafer to a finished thickness, after the bonding step; and a modified layer forming step of applying along a boundary between a device region and a peripheral surplus region of the first wafer a laser beam of such a wavelength as to be transmitted through the first wafer to form an annular modified layer inside the first wafer in the vicinity of the front surface of the first wafer, before the grinding step. * (“Nakamura US Patent 9269624 B2”) Discloses a wafer processing method including a wafer supporting step of mounting an adhesive film for die bonding on the back side of a wafer, attaching a dicing tape to the adhesive film, and supporting the peripheral portion of the dicing tape to an annular frame, wherein the wafer has already been divided into individual device chips along division lines formed on the front side or a break start point has already been formed inside the wafer along each division line, a protective film forming step of applying a water-soluble resin to the front side of the wafer and/or the peripheral portion of the adhesive film projecting from the outer circumference of the wafer, thereby forming a protective film from the water-soluble resin, and an adhesive film breaking step of expanding the dicing tape to thereby break the adhesive film along the individual device chips. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Aug 29, 2023
Application Filed
Jan 20, 2026
Non-Final Rejection mailed — §102
Apr 07, 2026
Interview Requested
Apr 14, 2026
Response Filed
Apr 14, 2026
Examiner Interview Summary
Apr 14, 2026
Applicant Interview (Telephonic)
Apr 28, 2026
Final Rejection (signed) — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
79%
Grant Probability
90%
With Interview (+10.5%)
3y 4m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 673 resolved cases by this examiner. Grant probability derived from career allowance rate.

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