DETAILED ACTION
Election/Restrictions
Applicant’s election of Species 2 (figure 3), corresponding to claims 1-7, 19 and 20, in the reply filed on 3/27/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al., US 12,500,131, in view of Cho et al., US 11,502,061, and Chen, US 12,412,869.
Regarding claim 1. Chiu (figures 2A & 2E) teaches a semiconductor package comprising:
a first redistribution layer 20;
a first semiconductor chip 21 above the first redistribution layer 20;
a second semiconductor 22 above the first semiconductor chip 21;
a second redistribution layer 23 above the second semiconductor 22;
a first connection structure 232 on the second redistribution layer 23;
a connection post 234 on the first connection structure 232; and
a connection interconnection layer 26 on the connection post 234,
wherein the connection interconnection layer 26 comprises a connection insulating layer 260 and a connection via (portion of 261 in via opening) extending through the connection insulating layer 260, and
wherein the second redistribution layer23 and the first redistribution layer 20 are electrically connected to each other through a wire 24a/24b; and
a width of a top surface of the connection via (portion of 261 in via opening) is greater than a width of a bottom surface of the connection via 261 (portion of 261 in via opening).
Chiu, which teaches an interposer, fails to teach the second semiconductor 22 is a chip.
Cho (figure 1A) teaches that interposer 300 may, or may not, have and circuit region including an semiconductor integrated circuit, therefore being an semiconductor chip.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the circuit region including an semiconductor integrated circuit of Cho in the invention of Chiu because Cho teaches the equivalence between an interposer not having a circuit region and one having a circuit region. By converting the interposer into a semiconductor chip the functionality of the device is increased. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Chiu fails to teach the connection interconnection layer is a single layer including the connection insulating layer and the connection via, the connection insulating layer having an integrated structure without a boundary therein.
Chen (figure 3A) teaches the connection interconnection layer 24 is a single layer including the connection insulating layer 240 and the connection via 241, the connection insulating layer 240 having an integrated structure without a boundary therein.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the connection interconnection layer of Chen in the invention of Chiu because it is a known equivalent. Chen states it contains at least one dielectric layer 240 (column 6, lines 29-33), therefore more than one layer is contemplated, which shows the equivalence between using a single layer or multiple layers.
With respect to claim 2, Choi teaches the first connection structure 232 comprises: a first connection pad 232; and though Choi fails to teach a second connection pad on the first connection pad 232, wherein the first connection pad and the second connection pad comprise different materials, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a second connection pad in the invention of Choi because they are conventionally known and used in the art as under bump metallization for things such as adhesion layers, seed layers, wetting layers, etc. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
As to claim 3, though Choi fails to teach a conductive structure on the connection interconnection layer, wherein the conductive structure comprises a first conductive pad and a second conductive pad disposed on the first conductive pad, wherein a width of the first conductive pad is substantially equal to a width of the second conductive pad, wherein the conductive structure further comprises an interface between the first conductive pad and the second conductive pad, and wherein the connection insulating layer is formed by a single deposition process, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this conductive structure in the invention of Chui because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Further, the fact that a single deposition process is used is not given any patentable weight because it is a process limitation in a product claim. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)
In re claim 4, Choi (figures 2A and 2E) teaches a wire connection structure 233 on the second redistribution layer 23, wherein the wire connection structure 233 is electrically connected to the first redistribution layer 20 through the wire 24a/24b.
Concerning claim 5, further comprising: a conductive structure 27 on the connection interconnection layer 26, wherein the conductive structure 27 comprises a first conductive pad 261 and a second conductive pad 270 on the first conductive pad 261.
Pertaining to claim 6, Choi (figures 2A and 2E) teaches a bottom surface of the connection via 261 is in contact with the connection post 234 and wherein a top surface of the connection via 261 is in contact with the first conductive pad 261.
In claim 7, Choi the first conductive pad 261 includes Ni or Cu (column 6, lines 8-9) and though Choi, which teaches an UBM layer (column 6, lines 26-29), fails to teach the second conductive pad includes Au, it would have been obvious to one of ordinary skill in the art at the time of the invention to use Au as the UBM in the invention of Choi because Au is a conventionally known and sued UBM. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Regarding claim 19, Choi (figures 2A & 2E) teaches a semiconductor package comprising:
a first redistribution layer 20;
a bump 211 on the first redistribution layer 20;
a first semiconductor chip 21 above the bump 211;
a second semiconductor 22 above the first semiconductor chip 21;
a second redistribution layer 23 above the second semiconductor 22;
a first connection structure 233 on the second redistribution layer 23;
a connection post 234 on the first connection structure 233;
a molding layer 25 on the first redistribution layer 20; and
a connection interconnection layer 26 on the connection post 234,
wherein the second redistribution layer 23 on the second semiconductor 22 is connected to the first redistribution layer 20 through a wire 24A/24B, and
wherein the molding layer 25 is in contact with the connection interconnection layer 26.
Chiu, which teaches an interposer, fails to teach the second semiconductor 22 is a chip.
Cho (figure 1A) teaches that interposer 300 may, or may not, have and circuit region including an semiconductor integrated circuit, therefore being an semiconductor chip.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the circuit region including an semiconductor integrated circuit of Cho in the invention of Chiu because Cho teaches the equivalence between an interposer not having a circuit region and one having a circuit region. By converting the interposer into a semiconductor chip the functionality of the device is increased. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Chiu fails to teach the connection interconnection layer comprises a connection insulating layer and a connection via extending through the connection insulating layer, the connection interconnection layer being a single layer including the connection insulating layer and the connection via, the connection insulating layer having an integrated structure without a boundary therein.
Chen (figure 3A) teaches the connection interconnection layer 24 comprises a connection insulating layer 240 and a connection via 241 extending through the connection insulating layer 240, the connection interconnection layer 24 is a single layer including the connection insulating layer 240 and the connection via 241, the connection insulating layer 240 having an integrated structure without a boundary therein.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the connection interconnection layer of Chen in the invention of Chiu because it is a known equivalent. Chen states it contains at least one dielectric layer 240 (column 6, lines 29-33), therefore more than one layer is contemplated, which shows the equivalence between using a single layer or multiple layers.
With respect to claim 20, wherein the first connection structure 233 comprises a first connection pad 233; and though Choi fails to teach a second connection pad on the first connection pad 232, wherein the first connection pad and the second connection pad comprise different materials, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a second connection pad in the invention of Choi because they are conventionally known and used in the art as under bump metallization for things such as adhesion layers, seed layers, wetting layers, etc. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teach various aspects of the invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 9/17/26
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