DETAILED ACTION
Election/Restrictions
Claims 3-6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method of manufacturing, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/23/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/29/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 14 is rejected under 35 U.S.C. 112(d), as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. In the present instance, claim 14 does not further limit claim 2 on which it is dependent on. Claim 2 states an upper limit of “30 atm %” but claim 14 implies that the range may extend beyond 30% with “10 atm % or more,” thereby failing to further limit claim 2.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (US 20220375521 A1), hereinafter “Yamazaki.”
Re: Claim 1, Yamazaki discloses a semiconductor memory device comprising (See Fig. 1: memory portion 1196; Fig. 11: memory portion 100 includes a 3D NAND memory circuit):
a stacked body having a plurality of conductive layers and a plurality of insulating layers alternately stacked one by one (Fig. 11: memory portion 100, insulator 114, conductor 153; ¶0120: a stacked-layer structure of inorganic films of a tungsten film and a silicon oxide film); and
a pillar extending in the stacked body in a stacking direction of the stacked body (Fig. 11: semiconductor 142), the pillar including a memory cell formed at each of intersections with the plurality of conductive layers (Fig. 13: shows a highlighted example of a memory cell MC[1] formed at an intersection with the plurality of conductive layers; ¶0127: the circuit illustrated in FIG. 4A includes the memory cells MC[1] to MC[n] and wirings WWL[1] to WWL[n], wirings RWL[1] to RWL[n], a wiring WBL, and a wiring RBL for controlling the memory cells; ¶0279: In the memory portion 100 of the data processing device illustrated in FIG. 13, the memory cell MC[1] included in the three-dimensional NAND memory circuit includes the transistor RTr, the transistor WTr, and the capacitor CS.), wherein the pillar includes:
a semiconductor layer extending in the stacking direction (Fig. 11: semiconductor 142),
a silicon oxynitride layer extending along a side wall of the semiconductor layer (Fig. 11: insulator 133; ¶0267: It is preferable to use silicon oxide or silicon oxynitride as the insulator 133),
a silicon nitride layer extending along a side wall of the silicon oxynitride layer (Fig. 11: Fig. 11: insulator 132; ¶0266: It is possible to use silicon nitride, silicon nitride oxide, or the like as the insulator 132), and
a silicon oxide layer extending along a side wall of the silicon nitride layer (Fig. 11: insulator 131; ¶0265: It is preferable to use silicon oxide, silicon oxynitride, or the like as the insulator 131),
wherein the silicon oxynitride layer has an average hydrogen concentration of 1×1020 atm/cc or less (¶0409: hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor, which is obtained by SIMS, is set lower than 1×1020 atoms/cm3, preferably lower than 1×1019 atoms/cm3).
Re: Claim 7, Yamazaki discloses the semiconductor memory device according to claim 1, and further discloses wherein the plurality of conductive layers include word lines (Fig. 11: transistors 800, conductors 153 and 155; ¶0127: The wiring WWL functions as a write word line, the wiring RWL functions as a read word line, the wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line.; ¶0241: the transistors 800 correspond to cell transistors that store data; ¶0250: The conductor 153 to the conductor 155 function as gates of the plurality of transistors 800 and wirings electrically connected to the gates.).
Re: Claim 8, Yamazaki discloses the semiconductor memory device according to claim 1, and further discloses wherein the plurality of conductive layers are formed of at least tungsten or molybdenum (¶0223: in order to ensure both conductivity and embeddability, it is preferable to use stacked layers of metal materials such as tungsten and aluminum as the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.).
Re: Claim 9, Yamazaki discloses the semiconductor memory device according to claim 1, and further discloses wherein the semiconductor memory device includes a three-dimensional nonvolatile memory (¶0021: three-dimensional NAND memory device).
Re: Claim 10, Yamazaki discloses the semiconductor memory device according to claim 1, and further discloses wherein the silicon oxide layer is a block insulating layer (¶0264: The insulator 131 functions as a gate insulating film of the transistors 800.).
Re: Claim 11, Yamazaki discloses the semiconductor memory device according to claim 1, and further discloses wherein the silicon nitride layer is a charge storage layer (¶0264: The insulator 132 functions as a charge accumulation layer of the transistors 800.).
Re: Claim 12, Yamazaki discloses the semiconductor memory device according to claim 1, and further discloses wherein the silicon oxynitride layer is a tunnel insulating layer (¶0264: The insulator 133 functions as a tunnel insulating film of the transistors 800.).
Re: Claim 13, Yamazaki discloses the semiconductor memory device according to claim 1, and further discloses wherein the silicon oxynitride layer has a hydrogen concentration of 1×1019 atm/cc or less in terms of average value (¶0409: hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor, which is obtained by SIMS, is set lower than 1×1020 atoms/cm3, preferably lower than 1×1019 atoms/cm3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US 20220375521 A1).
Re: Claim 2, Yamazaki discloses the semiconductor memory device according to claim 1.
Yamazaki discloses a 3D NAND memory structure (¶0021) having insulation layers (¶0264: insulation layers 131, 132, and 133) including a silicon oxynitride (SiON) layer which contains oxygen at a higher proportion than nitrogen (¶0227). Yamazaki also discloses using materials containing nitrogen in ¶0246 which states “Using such a material in some cases allows capture of hydrogen or water entering from a surrounding insulator or the like.” Yamazaki further discloses varying the concentration of nitrogen in order to stabilize electrical characteristics of a transistor (¶0408) and also varying the concentration of hydrogen for the same benefits (¶¶0409-0410).
Yamazaki differs from claim 2 in that it does not expressly disclose wherein a nitrogen concentration in the silicon oxynitride layer is in a range of 0 atm % or more and 30 atm % or less. However, Yamazaki teaches the general conditions of varying the oxygen and nitrogen composition of the SiON film such that selecting a nitrogen atm% range is a result-effective variable to the film quality as a barrier/tunneling layer (¶0404 and ¶0408).
In other words, the atm % of nitrogen concentration in a silicon oxynitride layer is a result-effective variable in the art, as Yamazaki explicitly recognizes that varying the nitrogen composition stabilizes electrical characteristics of a transistor.
Therefore, a person having ordinary skill in the art before the effective filing date, motivated by the objective to improve memory performance would have routinely experimented with known fabrication variables disclosed by Yamazaki in order to determine optimal values that increase the effectiveness of memory insulation layers beyond exemplified levels. Such routine optimization within the general conditions taught by Yamazaki would have naturally led to a nitrogen concentration in the silicon oxynitride layer having a range between 0 atm % or more and 30 atm % or less, as demonstrated by predictable enhancements in varying the nitrogen concentration in insulation materials (reasonable expectation of success given Yamazaki’s teachings on parameter effects). See MPEP § 2144.05(II)(“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation” (citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
Re: Claim 14, Yamazaki discloses the semiconductor memory device according to claim 2.
Yamazaki differs from claim 14 in that it does not expressly disclose wherein the nitrogen concentration in the silicon oxynitride layer is in a range of 10 atm % or more. However, Yamazaki teaches the general conditions of varying the oxygen and nitrogen composition of the SiON film such that selecting a nitrogen atm% range is a result-effective variable to the film quality as a barrier/tunneling layer.
In other words, the atm % of nitrogen concentration in a silicon oxynitride layer is a result-effective variable in the art, as Yamazaki explicitly recognizes that varying the nitrogen composition stabilizes electrical characteristics of a transistor.
Therefore, a person having ordinary skill in the art before the effective filing date, motivated by the objective to improve memory performance would have routinely experimented with known fabrication variables disclosed by Yamazaki in order to determine optimal values that increase the effectiveness of memory insulation layers beyond exemplified levels. Such routine optimization within the general conditions taught by Yamazaki would have naturally led to a nitrogen concentration in the silicon oxynitride layer having a range of 10 atm % or more, as demonstrated by predictable enhancements in varying the nitrogen concentration in insulation materials (reasonable expectation of success given Yamazaki’s teachings on parameter effects). See MPEP § 2144.05(II)(“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation” (citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Rajashekhar et al. (US 11239253 B2)– Figs. 5A-5G and Fig. 6
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898