DETAILED ACTION
Response to Arguments
In light of applicant’s amendment to claim 14, the rejection under 35 U.S.C. § 112(d) is withdrawn.
Applicant’s arguments with respect to claims 1, 2 and 7-14 have been considered but are moot in light of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2 and 7-14 are rejected under 35 U.S.C. 103 as being unpatentable over RAJASHEKHAR et al. (US 20200335516 A1), hereinafter “Rajashekhar,” in view of YAMAZAKI et al. (US 20220375521 A1, cited in previous office action), hereinafter “Yamazaki.”
Re: Independent Claim 1, Rajashekhar discloses a semiconductor memory device (Fig. 49A shows a memory device) comprising:
a stacked body having a plurality of conductive layers and a plurality of insulating layers alternately stacked one by one (Fig. 49A: alternating stack of insulating layers 32 and electrically conductive layer 46); and
a pillar extending in the stacked body in a stacking direction of the stacked body (Fig. 49A: vertical semiconductor channel 260), the pillar including a memory cell formed at each of intersections with the plurality of conductive layers (Fig. 37D shows a close up of the pillar structure in Fig. 49A which includes a charge storage layer 54 and electrically conductive layer 42/46; ¶0177: memory cell (comprising a portion of a charge storage layer 54 at a level of an electrically conductive layer 46)), wherein the pillar includes:
a semiconductor layer extending in the stacking direction (See Figs. 37D and 49A; Fig. 49A: vertical semiconductor channel 260), and
a memory layer extending along a sidewall and a bottom portion of the semiconductor layer, wherein the memory layer includes (Fig. 37D: memory film 50 extending along sidewall and a bottom portion of the semiconductor layer; Fig. 49A: memory film 50 extending along sidewall and bottom portion of layer 260):
a silicon oxynitride layer extending along a side wall of the semiconductor layer (Fig. 37D: tunneling dielectric layer 56; ¶0114: tunneling dielectric layer 56 may include silicon oxynitride),
a silicon nitride layer extending along a side wall of the silicon oxynitride layer (Fig. 37D: charge storage layer 54; ¶0111: charge storage layer 54 includes a silicon nitride layer), and
a silicon oxide layer extending along a side wall of the silicon nitride layer (Fig. 37D: blocking dielectric layer 52; ¶0110: may include silicon oxide),
…
However, Rajashekhar does not specifically disclose wherein the silicon oxynitride layer has an average hydrogen concentration of 1×1020 atm/cc or less.
In a similar field of endeavor, Yamazaki discloses wherein the silicon oxynitride layer has an average hydrogen concentration of 1×1020 atm/cc or less (¶0409: hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor, which is obtained by SIMS, is set lower than 1×1020 atoms/cm3, preferably lower than 1×1019 atoms/cm3).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have incorporated the teachings of Yamazaki regarding hydrogen concentrations in an oxide semiconductor in order to reduce reactions between oxygen and hydrogen as much as possible (See Yamazaki, ¶0409).
Re: Claim 2, the combination of Rajashekhar in view of Yamazaki discloses the semiconductor memory device according to claim 1.
Yamazaki discloses a 3D NAND memory structure (¶0021) having insulation layers (¶0264: insulation layers 131, 132, and 133) including a silicon oxynitride (SiON) layer which contains oxygen at a higher proportion than nitrogen (¶0227). Yamazaki also discloses using materials containing nitrogen in ¶0246 which states “Using such a material in some cases allows capture of hydrogen or water entering from a surrounding insulator or the like.” Yamazaki further discloses varying the concentration of nitrogen in order to stabilize electrical characteristics of a transistor (¶0408) and also varying the concentration of hydrogen for the same benefits (¶¶0409-0410).
Yamazaki differs from claim 2 in that it does not expressly disclose wherein a nitrogen concentration in the silicon oxynitride layer is in a range of 0 atm % or more and 30 atm % or less. However, Yamazaki teaches the general conditions of varying the oxygen and nitrogen composition of the SiON film such that selecting a nitrogen atm% range is a result-effective variable to the film quality as a barrier/tunneling layer.
In other words, the atm % of nitrogen concentration in a silicon oxynitride layer is a result-effective variable in the art, as Yamazaki explicitly recognizes that varying the nitrogen composition stabilizes electrical characteristics of a transistor.
Therefore, a person having ordinary skill in the art before the effective filing date, motivated by the objective to improve memory performance would have routinely experimented with known fabrication variables disclosed by Yamazaki in order to determine optimal values that increase the effectiveness of memory insulation layers beyond exemplified levels. Such routine optimization within the general conditions taught by Yamazaki would have naturally led to a nitrogen concentration in the silicon oxynitride layer having a range between 0 atm % or more and 30 atm % or less, as demonstrated by predictable enhancements in varying the nitrogen concentration in insulation materials (reasonable expectation of success given Yamazaki’s teachings on parameter effects). See MPEP § 2144.05(II)(“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation” (citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
Re: Claim 7, the combination of Rajashekhar in view of Yamazaki discloses the semiconductor memory device according to claim 1.
Rajashekhar further discloses wherein the plurality of conductive layers include word lines (¶0149: each electrically conductive layer 46 may be a word line).
Re: Claim 8, the combination of Rajashekhar in view of Yamazaki discloses the semiconductor memory device according to claim 1.
Rajashekhar further discloses wherein the plurality of conductive layers are formed of at least tungsten or molybdenum (Fig. 10: electrically conductive layers 46; ¶0145: The at least one elemental metal of the metallic fill material layer 46B may be selected, for example, from tungsten).
Re: Claim 9, the combination of Rajashekhar in view of Yamazaki discloses the semiconductor memory device according to claim 1.
Rajashekhar further discloses wherein the semiconductor memory device includes a three-dimensional nonvolatile memory (¶0074: three-dimensional NAND string memory device).
Re: Claim 10, the combination of Rajashekhar in view of Yamazaki discloses the semiconductor memory device according to claim 1.
Rajashekhar further discloses wherein the silicon oxide layer is a block insulating layer (¶0110: the blocking dielectric layer 52 may include silicon oxide).
Re: Claim 11, the combination of Rajashekhar in view of Yamazaki discloses the semiconductor memory device according to claim 1.
Rajashekhar further discloses wherein the silicon nitride layer is a charge storage layer (¶0111: charge storage layer 54 includes a silicon nitride layer).
Re: Claim 12, the combination of Rajashekhar in view of Yamazaki discloses the semiconductor memory device according to claim 1.
Rajashekhar further discloses wherein the silicon oxynitride layer is a tunnel insulating layer (¶0114: tunneling dielectric layer 56 may include silicon oxynitride).
Re: Claim 13, the combination of Rajashekhar in view of Yamazaki discloses the semiconductor memory device according to claim 1.
However, Rajashekhar does not specifically disclose wherein the silicon oxynitride layer has a hydrogen concentration of 1×1019 atm/cc or less in terms of average value.
Yamazaki further discloses wherein the silicon oxynitride layer has a hydrogen concentration of 1×1019 atm/cc or less in terms of average value (¶0409: hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor, which is obtained by SIMS, is set lower than 1×1020 atoms/cm3, preferably lower than 1×1019 atoms/cm3).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have incorporated the teachings of Yamazaki regarding hydrogen concentrations in an oxide semiconductor in order to reduce reactions between oxygen and hydrogen as much as possible (See Yamazaki, ¶0409).
Re: Claim 14, the combination of Rajashekhar in view of Yamazaki discloses the semiconductor memory device according to claim 1.
Yamazaki differs from claim 14 in that it does not expressly disclose wherein the nitrogen concentration in the silicon oxynitride layer is in a range of 10 atm % or more. However, Yamazaki teaches the general conditions of varying the oxygen and nitrogen composition of the SiON film such that selecting a nitrogen atm% range is a result-effective variable to the film quality as a barrier/tunneling layer.
In other words, the atm % of nitrogen concentration in a silicon oxynitride layer is a result-effective variable in the art, as Yamazaki explicitly recognizes that varying the nitrogen composition stabilizes electrical characteristics of a transistor.
Therefore, a person having ordinary skill in the art before the effective filing date, motivated by the objective to improve memory performance would have routinely experimented with known fabrication variables disclosed by Yamazaki in order to determine optimal values that increase the effectiveness of memory insulation layers beyond exemplified levels. Such routine optimization within the general conditions taught by Yamazaki would have naturally led to a nitrogen concentration in the silicon oxynitride layer having a range of 10 atm % or more, as demonstrated by predictable enhancements in varying the nitrogen concentration in insulation materials (reasonable expectation of success given Yamazaki’s teachings on parameter effects). See MPEP § 2144.05(II)(“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation” (citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
HIGUCHI et al. (US 20170117293 A1) – See Figs. 2, 4A-4C and 6 which show memory device structural details relevant to the current claims.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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