Attorney Docket Number: 043957.00014
Filing Date: 8/29/2023
Foreign Priority Date: 9/01/2022 (EP22193470.6)
Inventors: Endo et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments/arguments filed 2/04/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendments and arguments filed on 2/04/2026, responding to the Office action mailed 11/05/2025, have been entered. Applicant amended claims 1 and 17. The present Office action is made with all the suggested amendments being fully considered.
Response to Amendments/Arguments
Applicant’s amendments have overcome the claim rejections under 35 U.S.C. 112(b). Applicant’s arguments regarding the claim rejections of 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 11/05/2025, have been fully considered and are persuasive. Accordingly, the claim rejections of 35 U.S.C. 112 and 35 U.S.C. 103 are hereby withdrawn. However, upon further consideration, a new ground of rejection is made in view of 35 U.S.C. 103 regarding the newly amended claims. Accordingly, pending in this application are claims 1-20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 7, 11-13, and 16-18 are rejected under 35 U.S.C. 103 over Nomura (US 9137904 B2) in view of Yamagata (CN 114097075 A).
Regarding claim 1, Nomura (see, e.g., fig. 1) shows most aspects of the instant invention including an electronic component (e.g., module 1) comprising:
A circuit board (e.g., circuit board 2) having a top side (e.g., top side of circuit board 2) and a bottom side (e.g., bottom side of circuit board 2), with a circuit board (e.g., circuit board 2) area (e.g., area of circuit board 2) extending in a horizontal XY-plane a vertical Z-direction perpendicular to the XY- plane;
One or more dies (e.g., electronic components 3 on top surface of circuit board 2+ paragraph 14 “Examples of the electronic components 3 may include chip components, such as semiconductor elements that can be made of silicon or gallium arsenide, chip capacitors, and chip inductors”) coupled to the top side (e.g., top side of circuit board 2) of the circuit board (e.g., circuit board 2);
A package (e.g., resin layer 4b + resin layer 4a) having a top half (e.g., resin layer 4b) coupled to the top side (e.g., top side of circuit board 2) of the circuit board (e.g., circuit board 2) and that surrounds the one or more dies (e.g., electronic components 3 on top surface of circuit board 2 + paragraph 14 “Examples of the electronic components 3 may include chip components, such as semiconductor elements that can be made of silicon or gallium arsenide, chip capacitors, and chip inductors”), and a bottom half (e.g., resin layer 4a) coupled to the bottom side (e.g., bottom side of circuit board 2) of the circuit board (e.g., circuit board 2) so that a bottom surface (e.g., bottom surface of resin layer 4a) of the bottom half (e.g., resin layer 4a) forms a bottom of the electronic component (e.g., module 1);
A plurality of vertical columnar conductors (e.g., external connection conductors 6) that extend from the bottom side (e.g., bottom side of circuit board 2) of the circuit board (e.g., circuit board 2) through the bottom half (e.g., resin layer 4a) of the package (e.g., resin layer 4b + resin layer 4a);
Wherein the bottom half (e.g., resin layer 4a) of the package (e.g., resin layer 4b + resin layer 4a) comprises a solid support substance (see, e.g., paragraph 15 “Each of the resin layers 4a and 4b on both principal surfaces of the circuit board 2 can be made of epoxy resin.”), and the plurality of vertical columnar conductors (e.g., external connection conductors 6) are embedded in the solid support substance (see, e.g., paragraph 15 “Each of the resin layers 4a and 4b on both principal surfaces of the circuit board 2 can be made of epoxy resin.”);
Nomura (see, e.g., fig. 1) doesn’t explicitly show wherein the plurality of vertical columnar conductors have a total area within the circuit board that is greater than 4% of the circuit board area.
Yamagata (see, e.g., fig. 2), in a similar device to Nomura, teaches a plurality of conductors (e.g., conductor parts 11) have a total area within a board area (e.g., region 10 of ceramic substrate 100) that is greater than 4% (see, e.g., paragraph text “…in the first 1 area 10, the area ratio of the area covered by the conductor part 11 can be more than 50 %, more than 60 %, more than 70 %, more than 80 %, or more than 90 %”) of the board area (e.g., region 10 of ceramic substrate 100).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the substantially large conductor area configuration of Yamagata within the device of Nomura, in order to achieve the expected result of expanding the conductor profile within the device for an interface for additional/larger solder bumps, or for other various connectivity requirements. In addition, also note that while the current embodiment of Nomura doesn’t explicitly show the area of the circuit board occupied by the vertical columnar conductors (size of conductors or number of conductors, or size of circuit board) is greater than 4%, the area taken by the conductors 6 are rather prominent (see, e.g., fig. 1), and the exact utilized area becomes a design choice based on the layout and connectivity requirements dependent on the desired conductor-circuit board configuration necessary.
Regarding claim 2, Nomura (see, e.g., fig. 1) shows wherein the plurality of vertical columnar conductors (e.g., external connection conductors 6) are substantially evenly distributed in the circuit board area (e.g., area of circuit board 2).
Regarding claim 4, Nomura (see, e.g., fig. 1) shows wherein the circuit board area (e.g., area of circuit board 2) comprises a central section (see, e.g., central section in annotated fig. 1 below) and a peripheral section (see, e.g., peripheral section in annotated fig. 1 below) that surrounds the central section (see, e.g., central section in annotated fig. 1 below).
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Annotated Fig. 1
Regarding claim 5, Nomura (see, e.g., fig. 1) shows wherein an area of the plurality of the plurality of vertical columnar conductors (e.g., external connection --conductors 6) within the central section (see, e.g., central section in annotated fig. 1 above) is less than an area (e.g., note that the external connection conductors 6 lie entirely within the peripheral section in the annotated fig. 1 above) of the plurality of vertical columnar conductors (e.g., external connection conductors 6) within the peripheral section (see, e.g., peripheral section in annotated fig. 1 above).
Regarding claim 7, Nomura (see, e.g., fig. 1) shows wherein the plurality of vertical columnar conductors (e.g., external connection conductors 6) in the central section (see, e.g., central section in annotated fig. 1 above) are substantially evenly distributed (e.g., note that zero external connection conductors 6 lie within the central section) within the central section (see, e.g., central section in annotated fig. 1 above), and the plurality of vertical columnar conductors (e.g., external connection conductors 6) in the peripheral section (see, e.g., peripheral section in annotated fig. 1 above) are substantially evenly distributed (e.g., note one external connection conductor 6 within each peripheral section, hence evenly distributed) within the peripheral section (see, e.g., peripheral section in annotated fig. 1 above).
Claim 6 and 8 are rejected under 35 U.S.C. 103 over Nomura in view of Yamagata further in view of Takemura (US 20180364280 A1).
Regarding claim 6, Nomura in view of Yamagata fails to teach wherein an area of the plurality of vertical columnar conductors within the central section is greater than an area of the plurality of vertical columnar conductors within the peripheral section.
Takemura (see, e.g., fig. 2), in a similar device to Nomura in view of Yamagata, teaches wherein an area of the plurality of vertical columnar conductors (e.g., plurality of metal pins 11 + paragraph 36 “…corresponding to “columnar conductors…””) in a central section (see, e.g., annotated fig. 2 below) is greater than an area of the plurality of vertical columnar conductors (e.g., note the absence of columnar conductor metal pins 11 in the peripheral section) within a peripheral section (see, e.g., annotated fig. 2 below).
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Annotated Fig. 2
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the central section plurality of columnar conductors of Takemura within the device of Nomura in view of Yamagata, in order to achieve the expected result of providing an extended columnar conductor profile within the central portion of the device, as taught by Takemura. Note the plurality of columnar conductors within the central section is substantial relative to the plurality of columnar conductors within the peripheral section of Nomura (see, e.g., annotated fig. 1 above), hence the area of the plurality of columnar conductors within the central section after this modification would be greater than the area of the plurality of columnar conductors within the peripheral section.
In addition, it also would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to duplicate the vertical columnar conductors (hereinafter plurality of duplicated external connection conductors 6) of the peripheral section (see, e.g., annotated fig. 1 above) of Nomura numerous times within the central section, to achieve the expected result of providing additional conductive structures within the central section and increasing the conductive capabilities and efficiency within the device, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04. Note that duplicating the columnar conductors in this manner will result in a set of conductors substantially more numerous than that of the peripheral section (note that the central section is significantly larger than the peripheral section), and hence the area of the plurality duplicated conductors is greater than that of the plurality of vertical columnar conductors within the peripheral section.
Regarding claim 8, Nomura (see, e.g., fig. 1) shows the plurality of vertical columnar conductors (e.g., external connection conductors 6) in the peripheral section (see, e.g., peripheral section in annotated fig. 1 above) are substantially evenly distributed (e.g., note one external connection conductor 6 within each peripheral section, hence evenly distributed) within the peripheral section (see, e.g., peripheral section in annotated fig. 1 above).
Takemura (fig. 2) teaches the plurality of vertical columnar conductors in the central section (e.g., plurality of metal pins 11 + paragraph 36 “…corresponding to “columnar conductors…””) are substantially evenly distributed within the central section (see, e.g., central section in annotated fig. 2 above).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the evenly distributed plurality of columnar conductors of Takemura within the vertical columnar conductor layout of Nomura in view of Yamagata further in view of Takemura, in order to achieve the expected result of configuring an improved structural integrity and consistent electrical performance throughout the device.
Regarding claim 11, Nomura (see, e.g., fig. 1) shows the plurality of vertical columnar conductors (e.g., external connection conductors 6) are distributed substantially symmetrically with respect to a center of the circuit board area (e.g., area of circuit board 2).
Regarding claim 12, Nomura (see, e.g., fig. 1) shows one or more additional dies (e.g., electronic components 3 on bottom surface of circuit board 2 + paragraph 14 “Examples of the electronic components 3 may include chip components, such as semiconductor elements that can be made of silicon or gallium arsenide, chip capacitors, and chip inductors”) attached to the bottom side (e.g., bottom side of circuit board 2) of the circuit board (e.g., circuit board 2).
Regarding 13, Nomura (see, e.g., fig. 1) shows wherein the one or more additional dies (e.g., electronic components 3 on bottom surface of circuit board 2 + paragraph 14 “Examples of the electronic components 3 may include chip components, such as semiconductor elements that can be made of silicon or gallium arsenide, chip capacitors, and chip inductors”) are embedded in the solid support substance (see, e.g., paragraph 15 “Each of the resin layers 4a and 4b on both principal surfaces of the circuit board 2 can be made of epoxy resin.”).
Regarding claim 16, Nomura (see, e.g., fig. 1) shows wherein the plurality of vertical columnar conductors (e.g., external connection conductors 6) extend in the vertical z-direction (e.g., vertical direction).
Regarding claim 17, Nomura (see, e.g., fig. 1) shows most aspects of the instant invention including an electronic component (e.g., module 1) comprising:
A circuit board (e.g., circuit board 2) having an area (e.g., area of circuit board 2) that extends in a first plane;
One or more dies (e.g., electronic components 3 on top surface of circuit board 2 + paragraph 14 “Examples of the electronic components 3 may include chip components, such as semiconductor elements that can be made of silicon or gallium arsenide, chip capacitors, and chip inductors”) coupled to a first side (e.g., top side of circuit board 2) of the circuit board (e.g., circuit board 2);
A package (e.g., resin layer 4b + resin layer 4a) having a top half (e.g., resin layer 4b) coupled to the first side (e.g., top side of circuit board 2) of the circuit board (e.g., circuit board 2) and that surrounds the one or more dies (e.g., electronic components 3 on top surface of circuit board 2 + paragraph 14 “Examples of the electronic components 3 may include chip components, such as semiconductor elements that can be made of silicon or gallium arsenide, chip capacitors, and chip inductors”), and a bottom half (e.g., resin layer 4a) coupled to a second side (e.g., bottom side of circuit board 2) of the circuit board (e.g., circuit board 2) so that a bottom surface (e.g., bottom surface of resin layer 4a) of the bottom half (e.g., resin layer 4a) of the package (e.g., resin layer 4b + resin layer 4a) forms a bottom of the electronic component (e.g., module 1);
A plurality of vertical columnar conductors (e.g., external connection conductors 6) that extend from the bottom side (e.g., bottom side of circuit board 2) of the circuit board (e.g., circuit board 2) through the bottom half (e.g., resin layer 4a) of the package (e.g., resin layer 4b + resin layer 4a);
Wherein the bottom half (e.g., resin layer 4a) of the package (e.g., resin layer 4b + resin layer 4a) comprises a solid support substance (see, e.g., paragraph 15 “Each of the resin layers 4a and 4b on both principal surfaces of the circuit board 2 can be made of epoxy resin.”), and the plurality of vertical columnar conductors (e.g., external connection conductors 6) are embedded in the solid support substance (see, e.g., paragraph 15 “Each of the resin layers 4a and 4b on both principal surfaces of the circuit board 2 can be made of epoxy resin.”);
Nomura (see, e.g., fig. 1) doesn’t explicitly show wherein the plurality of vertical columnar conductors have a total area within the circuit board that is greater than 4% of the circuit board area.
Yamagata (see, e.g., fig. 2), in a similar device to Nomura, teaches a plurality of conductors (e.g., conductor parts 11) have a total area within a board area (e.g., region 10 of ceramic substrate 100) that is greater than 4% (see, e.g., paragraph text “…in the first 1 area 10, the area ratio of the area covered by the conductor part 11 can be more than 50 %, more than 60 %, more than 70 %, more than 80 %, or more than 90 %”) of the board area (e.g., region 10 of ceramic substrate 100).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the substantially large conductor area configuration of Yamagata within the device of Nomura, in order to achieve the expected result of expanding the conductor profile within the device for an interface for additional/larger solder bumps, or for other various connectivity requirements. In addition, also note that while the current embodiment of Nomura doesn’t explicitly show the area of the circuit board occupied by the vertical columnar conductors (size of conductors or number of conductors, or size of circuit board) is greater than 4%, the area taken by the conductors 6 are rather prominent (see, e.g., fig. 1), and the exact utilized area becomes a design choice based on the layout and connectivity requirements dependent on the desired conductor-circuit board configuration necessary.
Regarding claim 18, Nomura (see, e.g., fig. 1) shows wherein the plurality of vertical columnar conductors (e.g., external connection conductors 6) are substantially evenly distributed in the circuit board area (e.g., area of circuit board 2).
Claims 3 and 19 are rejected under 35 U.S.C. 103 over Nomura in view of Yamagata further in view of Ogawa (US 9832871 B2).
Regarding claim 3, Nomura in view of Yamagata fails to teach wherein the solid support substance comprises a plurality of trenches that extend from the bottom side of the circuit board to a bottom of the solid support substance.
Ogawa (see, e.g., fig. 4B), in a similar device to Nomura in view of Yamagata, teaches a plurality of trenches (e.g., cavities 11) that extend from the bottom side (e.g., bottom surface of wiring substrate 2) of a substrate (e.g., wiring substrate 2) to a bottom of a support substance (e.g., resist 10).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the trenches of Ogawa extending from the circuit board through the solid support substance of Nomura in view of Yamagata, in order to provide potential space for an interconnection structure with contact directly to the circuit board.
Regarding claim 19, Nomura in view of Yamagata fails to teach wherein the solid support substance comprises a plurality of trenches that extend from the bottom side of the circuit board to a bottom of the solid support substance.
Ogawa (see, e.g., fig. 4B), in a similar device to Nomura in view of Yamagata, teaches a plurality of trenches (e.g., cavities 11) that extend from the bottom side (e.g., bottom surface of wiring substrate 2) of a substrate (e.g., wiring substrate 2) to a bottom of a support substance (e.g., resist 10).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the trenches of Ogawa extending from the circuit board through the solid support substance of Nomura in view of Yamagata, in order to provide potential space for an interconnection structure with contact directly to the circuit board.
Claims 9-10 and 20 are rejected under 35 U.S.C. 103 over Nomura in view of Yamagata further in view of Hino (US 20110180809 A1).
Regarding claim 9, Nomura in view of Yamagata fails to teach wherein a smallest horizontal distance between two adjacent columnar conductors of the plurality of vertical columnar conductors is greater than 0.3 mm.
Hino (see, e.g., fig. 3), in a similar device to Nomura in view of Yamagata, teaches a length of a circuit board (e.g., circuit board 2) is greater than .3 mm (see, e.g., paragraph 56 “The circuit board 2 has… a long-side length of 10 to 150 mm”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the circuit board length of Hino within the circuit board of Nomura in view of Yamagata, as the side-length is dependent on the mounted semiconductor components (see, e.g., paragraph 56 “The long-side length is changed optionally depending on the number of semiconductor elements mounted”). Note that the plurality of vertical columnar conductors are placed substantially on opposing ends of the circuit board, and a circuit board length of 10 mm with conductors placed on opposite ends of the circuit board would result in a distance between the conductors substantially greater than .3 mm.
Regarding claim 10, Nomura in view of Yamagata fails to teach wherein a greatest horizontal distance between two adjacent columnar conductors of the plurality of vertical columnar conductors is less than 10 mm.
Hino (see, e.g., fig. 3), in a similar device to Nomura in view of Yamagata, teaches a length of a circuit board (e.g., circuit board 2) is 10 mm (see, e.g., paragraph 56 “The circuit board 2 has… a long-side length of 10…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the circuit board length of Hino within the circuit board of Nomura in view of Yamagata, as the side-length is dependent on the mounted semiconductor components (see, e.g., paragraph 56 “The long-side length is changed optionally depending on the number of semiconductor elements mounted”). Note that the plurality of vertical columnar conductors are placed substantially on opposing ends of the circuit board, and a circuit board length of 10 mm with conductors placed on opposite ends of the circuit board would result in a distance between the conductors being less than 10 mm (note 10 mm is the total length of the circuit board and the columnar conductors of Nomura do not lie on the absolute edge (see fig. 1 of Nomura)).
Regarding claim 20, Nomura in view of Yamagata fails to teach wherein a horizontal distance between two adjacent columnar conductors of the plurality of vertical columnar conductors is greater than 0.3 mm and less than 10 mm.
Hino (see, e.g., fig. 3), in a similar device to Nomura in view of Yamagata, teaches a length of a circuit board (e.g., circuit board 2) is greater than .3 mm (see, e.g., paragraph 56 “The circuit board 2 has… a long-side length of 10 to 150 mm”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the circuit board length of Hino within the circuit board of Nomura in view of Yamagata, as the side-length is dependent on the mounted semiconductor components (see, e.g., paragraph 56 “The long-side length is changed optionally depending on the number of semiconductor elements mounted”). Note that the plurality of vertical columnar conductors are placed substantially on opposing ends of the circuit board, and a circuit board length of 10 mm with conductors placed on opposite ends of the circuit board would result in a distance between the conductors substantially greater than .3 mm, while being less than 10 mm (note 10 mm is the total length of the circuit board and the columnar conductors of Nomura do not lie on the absolute edge (see fig. 1 of Nomura)).
Claim 14 is rejected under 35 U.S.C. 103 over Nomura in view of Yamagata further in view of Talledo (US 20210343658 A1).
Regarding claim 14, Nomura in view of Yamagata fails to teach wherein the one or more dies comprise a MEMS die and the one or more additional dies comprises an ASIC die.
Talledo (see, e.g., fig. 1A), in a similar device to Nomura in view of Yamagata, teaches a die (e.g., die 110) can comprise a MEMS die or an ASIC die (see, e.g., paragraph 27 “The die 110 may be an application specific integrated circuit (ASIC), a processor, a sound sensor, a temperature sensor, a micro-electro mechanical system (MEMS) die”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the MEMS and ASIC die within the dies of Nomura in view of Yamagata, in order to provide both sensing/pressure capabilities within the chip or customized application-based capabilities within the chip, respectively.
Claim 15 is rejected under 35 U.S.C. 103 over Nomura in view of Yamagata further in view of Wu (US 20230387039 A1).
Regarding claim 15, Nomura in view of Yamagata fails to teach wherein the one or more dies comprise a MEMS die and the one or more additional dies comprise a microcontroller die.
Wu (see, e.g., fig. 1), in a similar device to Nomura in view of Yamagata, teaches a die (e.g., integrated circuit die 50) can comprise a MEMS die or a microcontroller die (see, e.g., paragraph 11 “The integrated circuit die 50 may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the MEMS and microcontroller die within the dies of Nomura in view of Yamagata, in order to prove both sensing/pressure capabilities and the flexible functionality capabilities within the chip, respectively.
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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