Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Regarding claim 1, Seong discloses a semiconductor device comprising: a substrate (Fig. 6A, 110) including a cell region (Fig. 1, CR) and a connection region around the cell region (See attached figure); a plurality of cell device isolation layers (Fig. 6A, 116) in the cell region of the substrate, the plurality of cell device isolation layers defining a plurality of active regions (118) in the cell region of the substrate; a connection region isolation layer (118 in connection region) in the substrate, the connection region being defined by the connection region isolation layer (Shown in Fig. 6A); a cell word line (Fig. 1, WL; Fig. 6B, 120) extending across the plurality of active regions (Shown in Fig. 1) in a first horizontal direction (X direction) on the cell region of the substrate; a cell bit line (Fig. 1, BL; Figs. 6A-B, 140) including a cell metallic conductive pattern (first metal conductive pattern 145 in the cell region), the cell metallic conductive pattern extending on the cell region of the substrate in a second horizontal direction (Para. 43 "The first metal conductive layer, the second metal conductive layer, and the insulation capping layer are etched, thereby forming a plurality of bit lines 147 each including a first metal conductive pattern 145 and a second metal conductive pattern 146, which have a line shape"; para. 45 "a plurality of bit lines 147... may each extend lengthwise in the second horizontal direction (Y direction)"; the bit lines extend in a second horizontal direction and the cell metallic conductive patterns are part of the bit lines), the second horizontal direction intersecting the first horizontal direction (X direction intersects the Y direction); and a connection bit line (Fig. 1, BL in the connection region; Figs. 6A-B, comprises 146, 145 and 132 in the connection region) including a connection metallic conductive pattern (first metal conductive pattern 145 in the connection region), the connection metallic
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conductive pattern extending in the second horizontal direction on the connection region of the substrate (Para. 43 "The first metal conductive layer, the second metal conductive layer, and the insulation capping layer are etched, thereby forming a plurality of bit lines 147 each including a first metal conductive pattern 145 and a second metal conductive pattern 146"; para. 45 "a plurality of bit lines 147... may each extend lengthwise in the second horizontal direction (Y direction)"; the bit lines extend in a second horizontal direction and the cell metallic conductive patterns are part of the bit lines), wherein a top surface of the connection region isolation layer is located at a higher vertical level than top surfaces of the plurality of cell device isolation layers, a top surface of the connection bit line is located at a vertical level that is equal to or lower than a top surface of the cell bit line (See attached figure), a height of the connection metallic conductive pattern in a vertical direction is equal to or greater than a height of the cell metallic conductive pattern in the vertical direction (Fig. 6A shows height of connection metallic conductive pattern being equal to height of cell metallic conductive pattern). However, Seong does not disclose a thickness of the connection bit line in the vertical direction being less than a thickness of the cell bit line in the vertical direction.
On the other hand, Lee discloses a thickness of the connection bit line (Fig 4C, 130_1) in the vertical direction is less than a thickness of the cell bit line in the vertical direction (130_2). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Seong according to the teachings of Lee such that the thickness of the connection bit line in the vertical direction would be less than a thickness of the cell bit line in the vertical direction, in order to reduce material costs and design complexity by not burying the connection bit lines into the active regions, since they are only designed to carry signals across the device.
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Regarding claim 2, Seong discloses the top surface of the connection region isolation layer is located at a higher vertical level than the substrate in the cell region (See attached figure).
Regarding claim 3, Lee discloses wherein the cell bit line further includes a cell conductive semiconductor pattern (Fig. 4C, 141 in 130_1; Para. 65 "the first conductive layer 141 may include a doped semiconductor material") between the cell metallic conductive pattern (142 in 130_1) and the substrate (100), the connection bit line further includes a connection conductive semiconductor pattern (141 in 130_2) between the connection metallic conductive pattern (132 in 130_2) and the substrate, and a top surface of the connection conductive semiconductor pattern is located at a vertical level that is equal to or lower than a top surface of the cell conductive semiconductor pattern (Shown in Fig. 4C).
Regarding claim 4, Seong discloses wherein a bottom surface of the connection bit line is located at a vertical level that is equal to or higher than a bottom surface of the cell bit line (Shown in Fig. 6A).
Regarding claim 5, Lee discloses where the thickness of the connection bit line (Fig. 4C, 130_2) in the vertical direction is a distance from a bottom surface of the connection conductive semiconductor pattern (141 in 130_2; Para. 65 "the first conductive layer 141 may include a doped semiconductor material") to a top surface of the connection metallic conductive pattern (second conductive layer 142 in 130_2), the top surface of the connection metallic conductive pattern is the top surface of the connection bit line (Shown), the thickness of the cell bit line (130_1) in the vertical direction is a distance from a bottom surface of the cell conductive semiconductor pattern (141 in 130_1; Para. 65 "the first conductive layer 141 may include a doped semiconductor material") to a top surface of the cell metallic conductive pattern (second conductive layer 142 in 130_1), and the top surface of the cell metallic conductive pattern is the top surface of the cell bit line (Shown).
Regarding claim 6, Seong discloses further comprising: a connection insulating layer (second insulating pattern 114 in connection region) between the substrate in the connection region and the connection bit line, wherein at least a portion of a bottom surface of the connection metallic conductive pattern is in direct contact with a top surface of the connection insulating layer (Shown in Fig. 6A).
Regarding claim 7, Seong discloses wherein the plurality of active regions include an outer active region and at least one inner active region (See attached figure), the outer active region is adjacent to the connection region isolation layer, the at least one inner active region is spaced apart from the connection region isolation layer with the outer active region therebetween, and a top surface of at least a portion of the cell bit line on the outer active region has a vertical level that is equal to or lower
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than a top surface of a remaining portion of the cell bit line disposed on the inner active region (Shown).
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Regarding claim 18, Seong discloses a semiconductor device comprising: a substrate (Fig. 6A, 110) including a cell region (Fig. 1, CR) and a connection region around the cell region (See attached figure); a cell device isolation layer (Fig. 6A, 116) in the cell region of the substrate, the cell device isolation layer defining an active region (118) in the cell region of the substrate; a connection region isolation layer (118 in connection region) in the substrate, the connection region being defined by the connection region isolation layer (Shown in Fig. 6A); a cell word line (Fig. 1, WL; Fig. 6B, 120) extending across the active region (Shown in Fig. 1) in a first horizontal direction (X direction) on the cell region of the substrate; a cell bit line (Fig. 1, BL; Figs. 6A-B, 140) extending on the cell region of the substrate in a second horizontal direction (Y direction), the second horizontal direction intersecting the first horizontal direction (X direction intersects the Y direction); and a connection bit line (Fig. 1, BL in the connection region; Figs. 6A-B, comprises 146, 145 and 132 in the connection region) extending in the second horizontal direction on the connection region of the substrate (Shown in Fig. 1), wherein a top surface of the connection region isolation layer is located at a higher vertical level than a top surface
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of the cell device isolation layer (See attached figure), wherein the cell bit line includes a cell conductive semiconductor pattern (conductive semiconductor pattern 132 in cell region) and a cell metallic conductive pattern (first metal conductive pattern 145 in the cell region) on the cell conductive semiconductor pattern (Fig. 6A shows 145 on 132 in the cell region), the connection bit line includes a connection conductive semiconductor pattern (conductive semiconductor pattern 132 in connection region) and a connection metallic conductive pattern (first metal conductive pattern 145 in the connection region) on the connection conductive semiconductor pattern (Fig. 6A shows 145 on 132 in the connection region), the cell conductive semiconductor pattern and the connection conductive semiconductor pattern each include polysilicon (Para. 45 "The conductive semiconductor pattern 132 may include doped polysilicon"), a top surface of the connection conductive semiconductor pattern is located at a vertical level that is equal to or lower than a top surface of the cell conductive semiconductor pattern (Shown in fig. 6A), a vertical level difference between a top surface of the connection metallic conductive pattern and a top surface of the cell metallic conductive pattern is equal to or less than a vertical level difference between a bottom surface of the connection metallic conductive pattern and a bottom surface of the cell metallic conductive pattern (Shown in fig. 6A; the vertical level difference between a top surface of 145 in the connection region and 145 in the cell region is 0, the vertical level difference between a bottom surface of 145 in the connection region and 145 in the cell region is 0, therefore the level differences are equal). However, Seong does not disclose the thickness of the connection bit line in the vertical direction being less than a thickness of the cell bit line in the vertical direction.
On the other hand, Lee discloses a thickness of the connection bit line (Fig 4C, 130_1) in the vertical direction is less than a thickness of the cell bit line in the vertical direction (130_2). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Seong according to the teachings of Lee such that the thickness of the connection bit line in the vertical direction would be less than a thickness of the cell bit line in the vertical direction, in order to reduce material costs and design complexity by not burying the connection bit lines into the active regions, since they are only designed to carry signals across the device.
Regarding claim 19, Lee discloses wherein a bottom surface of the connection conductive semiconductor pattern (Fig. 4C, 141 in 130_2) is located at a vertical level that is equal to or higher than a bottom surface of the cell conductive semiconductor pattern (Fig. 4C shows the bottom surface of 141 in 130_2 being at a higher level than a bottom surface of 141 in 130_1), where the thickness of the connection bit line (Fig. 4C, 130_2) in the vertical direction is a distance from a bottom surface of the connection conductive semiconductor pattern (141 in 130_2; Para. 65 "the first conductive layer 141 may include a doped semiconductor material") to a top surface of the connection metallic conductive pattern (second conductive layer 142 in 130_2), the top surface of the connection metallic conductive pattern is the top surface of the connection bit line (Shown), the thickness of the cell bit line (130_1) in the vertical direction is a distance from a bottom surface of the cell conductive semiconductor pattern (141 in 130_1; Para. 65 "the first conductive layer 141 may include a doped semiconductor material") to a top surface of the cell metallic conductive pattern (second conductive layer 142 in 130_1), and the top surface of the cell metallic conductive pattern is the top surface of the cell bit line (Shown).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10-13 and 15-16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Seong (US 20210193664 A1).
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Regarding claim 10, Seong discloses a semiconductor device comprising: a substrate (Fig. 6A, 110) including a cell region (Fig. 1, CR) and a connection region around the cell region (See attached figure); a plurality of cell device isolation layers (Fig. 6A, 116) in the cell region of the substrate, the plurality of cell device isolation layers defining a plurality of active regions (118) in the cell region of the substrate; a cell word line (Fig. 1, WL; Fig. 6B, 120) extending across the plurality of active regions (Shown in Fig. 1) in a first horizontal direction (X direction) on the cell region of the substrate; a cell bit line (Fig. 1, BL; Figs. 6A-B, 140) including a cell conductive semiconductor pattern (conductive semiconductor pattern 132 in cell region), the cell conductive semiconductor pattern extending on the cell region of the substrate in a second horizontal direction (Para. 45 "A plurality of bit line structures 140 including a plurality of bit lines 147 and a plurality of insulation capping lines 148 may each extend lengthwise in the second horizontal direction (Y direction).... each of the plurality of bit line structures 140 may further include a conductive semiconductor pattern 132"; para. ""; the bit lines extend in a second horizontal direction and the cell conductive semiconductor patterns are part of the bit lines), the second horizontal direction intersecting the first horizontal direction (X direction intersects the Y direction); and a connection bit line (Fig. 1, BL in the connection region; Figs. 6A-B, comprises 146, 145 and 132 in the connection region) including a connection conductive semiconductor pattern (conductive semiconductor pattern 132 in connection region), the connection conductive semiconductor pattern extending in the second horizontal direction on the connection region of the substrate (Para. 43 "The first metal conductive layer, the second metal conductive layer, and the insulation capping layer are etched, thereby forming a plurality of bit lines 147 each including a first metal conductive pattern 145 and a second metal conductive pattern 146"; para. 45 "a plurality of bit lines 147... may each extend lengthwise in the second horizontal direction (Y direction)"; the bit lines extend in a second horizontal direction and the cell metallic conductive patterns are part of the bit lines), wherein the connection conductive semiconductor pattern includes portion having a lower height in a vertical direction than a height of the cell conductive semiconductor pattern in the vertical direction (arbitrary bottom portion of connection conductive semiconductor pattern is a portion having a lower height than the cell conductive semiconductor pattern 132; Examiner notes that the term “a portion” is sufficiently broad as to apply to any arbitrary portion of the connection conductive semiconductor pattern that may a have a lower height than a height of the cell conductive semiconductor pattern).
Regarding claim 11, Seong discloses wherein a top surface of the connection conductive semiconductor pattern is located at a vertical level that is equal to or lower than a top surface of the cell conductive semiconductor pattern (Shown in Fig. 6A).
Regarding claim 12, Seong discloses wherein a bottom surface of the connection conductive semiconductor pattern is located at a vertical level that is equal to or higher than a bottom surface of the cell conductive semiconductor pattern (Shown in Fig. 6A).
Regarding claim 13, Seong discloses wherein the cell bit line includes a cell metallic conductive pattern (first metal conductive pattern 145 in the cell region), the connection bit line includes a connection metallic conductive pattern (first metal conductive pattern 145 in the connection region), and a bottom surface of the connection metallic conductive pattern is located at a vertical level that is equal to or lower than a bottom surface of the cell metallic conductive pattern (Shown in Fig. 6A).
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Regarding claim 15, Seong discloses wherein a height of the connection bit line in the vertical direction is less than a height of the cell bit line in the vertical direction (See attached figure).
Regarding claim 16, Seong discloses further comprising: a connection region isolation layer (Fig. 6A, 116 in connection region) in the connection region of the substrate, wherein a top surface of the connection region isolation layer is located at a higher vertical level than the substrate in the cell region (Shown in Fig. 6A).
Response to Arguments
Applicant’s arguments, see pgs. 12-13, filed 7/8/2026, with respect to the rejection(s) of claim(s) 1-7 and 18-20 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art.
While Seong does not directly teach the new limitations of amended claims 1 and 18 concerning the difference in thickness between the connection bit line and the cell bit line, Lee teaches a connection bit line and a cell bit line having different vertical thicknesses. Like the instant application, Lee’s connection bit lines are not taught to connect to the active memory cells in their region, but rather carry signals across the device. For this reason, Lee discloses a simplified connection bit line structure where the connection bit lines do not penetrate as deeply into the active region or other underlying layers.
Applicant’s arguments, see pgs. 11-12, filed 7/8/2026, with respect to the rejection(s) of claim(s) 10-16 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a new interpretation of the art. Specifically, Seong can reasonably be interpreted to disclose the “wherein the connection conductive semiconductor pattern includes a portion having a lower height in a vertical direction than a height of the cell conductive semiconductor pattern in the vertical direction”. The language “a portion” is sufficiently broad that any arbitrary portion of the connection conductive semiconductor pattern can chosen such that it has a lower height in the vertical direction than a height of the cell conductive semiconductor pattern. Claims 10-16 are therefore still anticipated by Seong.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
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/S.J.S./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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