DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 10, 11, 25 and 30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE (US 20130001573).
Regarding claim 1, LEE discloses a vertical transistor comprising:
a substrate (substrate 310, see fig 8, para 126);
a lower electrode on the substrate and comprising a metal material (SE3 can be Al and is directly on 310, see fig 8, para 127);
a carbon thin film that is conductive and is on the lower electrode (graphene layer 360 which is conductive carbon and is directly on SE3, see fig 8, para 157 and 54);
an oxide semiconductor layer on the carbon thin film (340 can be an oxide semiconductor and is directly on 360, see fig 8);
a gate electrode apart from the oxide semiconductor layer (gate electrode GE3 is spaced apart from 350, see fig 8, para 125);
a gate insulating layer between the oxide semiconductor layer and the gate electrode (350 is between GE3 and 340, see fig 8); and
an upper electrode arranged on the oxide semiconductor layer (upper electrode 330 is directly on 340, see fig 8, para 125),
wherein the lower electrode, the carbon thin film, the oxide semiconductor layer, and the upper electrode are arranged in a direction perpendicular to the substrate (SE3, 360, 340 and 330 are all arranged above the top surface of 310, see fig 8).
Regarding claim 3, LEE discloses the vertical transistor of claim 1, wherein the lower electrode, the carbon thin film, the oxide semiconductor layer, and the upper electrode are sequentially stacked without any intervening layer (SE3 is in direct contact with 360, 360 is in direct contact with 340, and 340 is in direct contact with 330, see fig 8).
Regarding claim 4, LEE discloses the vertical transistor of claim 1, wherein the lower electrode has a width greater than or equal to a width of the oxide semiconductor layer (SE3 is wider than 340, see fig 8).
Regarding claim 10, LEE discloses the vertical transistor of claim 1, wherein the lower electrode comprises at least one metal selected from among tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), titanium (Ti), molybdenum (Mo), chromium (Cr), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), silver (Ag), gold (Au), aluminum (Al), copper (Cu) (SE3 can be Cu, see fig 8, para 127), stannum (Sn), vanadium (V), ruthenium (Ru), platinum (Pt), zinc (Zn), and magnesium (Mg).
Regarding claim 11, LEE discloses the vertical transistor of claim 1, wherein the carbon thin film comprises at least one of graphene (360 can be graphene, see fig 8, para 156), fullerene, and a carbon nanotube.
Regarding claim 25, LEE discloses the vertical transistor of claim 1, wherein a plane of an upper surface of the substrate is parallel to a plane of a lower surface of the carbon thin film (the upper surface of substrate 310 is a horizontal plane, which is coplanar with the lowermost horizontal surface of carbon thin film 360, see fig 8, para 157 and 126).
Regarding claim 30, LEE discloses the vertical transistor of claim 1, wherein an imaginary vertical line extending perpendicularly from an upper surface of the substrate intersects the lower electrode, the carbon thin film, the oxide semiconductor layer, and the upper electrode (a vertical line can be drawn up from the substrate that intersects Se3, 360, 340 and 330, see fig 8 and figure I below).
PNG
media_image1.png
756
818
media_image1.png
Greyscale
Figure I: LEE figure 8 with added annotations.
Claim(s) 1-2, 4-12, 25 and 28-29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YAMAZAKI (US 20220262438).
Regarding claim 1, YAMAZAKI discloses a vertical transistor comprising:
a substrate (substrate 121, see fig 3, para 137);
a lower electrode on the substrate and comprising a metal material (122 can be metal, see fig 1-7, para 250);
a carbon thin film that is conductive and is on the lower electrode (125 can be graphene, see para 232-234, and is directly on 122, see fig 3 and 7, para 140);
an oxide semiconductor layer on the carbon thin film (127 can be an oxide semiconductor, and is at least indirectly on 125, see fig 1-7, para 170);
a gate electrode apart from the oxide semiconductor layer (the gate electrode comprising SG and WWL, see fig 3, para 145);
a gate insulating layer between the oxide semiconductor layer and the gate electrode (insulators 124 and 126 separate WWL from 127, see fig 7A, para 144); and
an upper electrode arranged on the oxide semiconductor layer (upper conductor BL, see fig 3, para 369),
wherein the lower electrode, the carbon thin film, the oxide semiconductor layer, and the upper electrode are arranged in a direction perpendicular to the substrate (122, 125, 127 and BL are arranged above the substrate 121, see fig 3).
Regarding claim 2, YAMAZAKI discloses the vertical transistor of claim 1, wherein the gate insulating layer entirely surrounds side surfaces of the oxide semiconductor layer (124 entirely surrounds 125, see fig 5A, para 143).
Regarding claim 4, YAMAZAKI discloses the vertical transistor of claim 1, wherein the lower electrode has a width greater than or equal to a width of the oxide semiconductor layer (122 is wider than 127, see fig 3).
Regarding claim 5, YAMAZAKI discloses the vertical transistor of claim 1, further comprising:
a mold insulating layer (insulator 123, see fig 3, para 132) on the lower electrode and defining an opening (the opening in 123 in which 124, 125, 126 and 127 are disposed, see fig 3 and 7, para 132),
wherein the carbon thin film is on a bottom portion of the opening (125 is on a bottom surface of the opening in 123, see fig 3 and 7, para 139).
Regarding claim 6, YAMAZAKI discloses the vertical transistor of claim 5, wherein
the oxide semiconductor layer comprises a first vertical extension on a first sidewall of the opening (a vertical portion of 127 on the left side of fig 3 and 7A, see para 140),
a second vertical extension on a second sidewall of the opening (a vertical portion of 127 on the right side of fig 3 and 7A, see para 140), and
a lower portion connected between the first vertical extension and the second vertical extension (the lower portion of 127 which extends horizontally at the bottom of fig 3 and 7A, see para 140).
Regarding claim 7, YAMAZAKI discloses the vertical transistor of claim 6, wherein
the gate electrode extends in a second horizontal direction (WWL extends horizontally, see fig 3) and comprises a first gate electrode corresponding to the first vertical extension (first electrode WWL1 which surrounds the left portion of 127, see fig 3, para 145) and a second gate electrode (second electrode WWL2 which surrounds the right portion of 127, see fig 3, para 145) corresponding to the second vertical extension, and
the gate insulating layer comprises a first gate insulating layer corresponding to the first gate electrode (124 is surrounded by WWL1, see fig 3 and 7, para 140) and a second gate insulating layer corresponding to the second gate electrode (126 is surrounded by WWL2, see fig 3 and 7, para 140).
Regarding claim 8, YAMAZAKI discloses the vertical transistor of claim 6, wherein
the gate electrode comprises a first gate electrode and a second gate electrode that are arranged to face each other and are configured to be driven electrically independently (WWL1 and WWL2 face each other in the vertical direction, and can be driven separately, see para 142 and figs 2-3), and
the gate insulating layer comprises a first gate insulating layer corresponding to the first gate electrode (124 is surrounded by WWL1, see fig 3 and 7, para 140) and a second gate insulating layer corresponding to the second gate electrode (126 is surrounded by WWL2, see fig 3 and 7, para 140).
Regarding claim 9, YAMAZAKI discloses the vertical transistor of claim 6, wherein the oxide semiconductor layer has a U-shaped structure (127 has a u-shaped structure, see fig 3 and 7).
Regarding claim 10, YAMAZAKI discloses the vertical transistor of claim 1, wherein the lower electrode comprises at least one metal selected from among tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), titanium (Ti), molybdenum (Mo), chromium (Cr), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), silver (Ag), gold (Au), aluminum (Al), copper (Cu) (122 can be Cu, see fig 3, para 253), stannum (Sn), vanadium (V), ruthenium (Ru), platinum (Pt), zinc (Zn), and magnesium (Mg).
Regarding claim 11, YAMAZAKI discloses the vertical transistor of claim 1, wherein the carbon thin film comprises at least one of graphene (125 can be graphene, see para 232-234), fullerene, and a carbon nanotube.
Regarding claim 12, YAMAZAKI discloses the vertical transistor of claim 1, wherein the oxide semiconductor layer comprises at least one selected from among InGaZnO (127 can be IGZO, see fig 3 and 7, para 362), ZnO, ZrInZnO, InZnO, ZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2Os, In2O3SnO2, MgZnO, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2Os, TiSrO3, ZIO, IGO.
Regarding claim 25, YAMAZAKI discloses the vertical transistor of claim 1, wherein a plane of an upper surface of the substrate is parallel to a plane of a lower surface of the carbon thin film (the upper surface of the substrate 121 is a horizontal plane, and a lower surface of 125 is also a horizontal plane, see fig 3, 7 and 17C, para 140).
Regarding claim 28, YAMAZAKI discloses the vertical transistor of claim 1, wherein the oxide semiconductor layer and the gate insulating layer share a vertical surface extending perpendicular to an upper surface of the substrate (oxide semiconductor 127 and gate insulator 126 share a vertical surface that is perpendicular to the horizontal top surface of 121, see fig 3 and 7, para 140).
Regarding claim 29, YAMAZAKI discloses the vertical transistor of claim 1, wherein the oxide semiconductor layer is between the lower electrode and the upper electrode (a line can be drawn from the lower electrode 122 to the upper electrode BL that passes through 127, see fig 3, para 140).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 20130001573) in view of SANDHU (US 9177872).
Regarding claim 26, LEE discloses the vertical transistor of claim 1.
LEE fails to explicitly disclose a device, wherein an upper surface of the oxide semiconductor layer is same as a lower surface of the upper electrode.
SANDHU teaches a device, wherein an upper surface of the oxide semiconductor layer is same as a lower surface of the upper electrode (the upper surface of the semiconductor channel 144 is the same as the lower surface of the upper electrode, see fig 1, para 24 and 36).
LEE and SANDHU are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the coplanar semiconductor layer and upper electrode of SANDHU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the coplanar semiconductor layer and upper electrode of SANDHU in order to make a device with high density (see SANDHU para 8).
Claim(s) 27, 31 and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 20130001573) in view of KIM (US 20060244361).
Regarding claim 27, LEE discloses The vertical transistor of claim 1, wherein the carbon thin film, the oxide semiconductor layer, and the gate insulating layer meet at a common vertex.
LEE fails to explicitly disclose a device
KIM teaches a device , wherein the carbon thin film, the oxide semiconductor layer, and the gate insulating layer meet at a common vertex (the semiconductor channel 44, the gate insulator 40 and the carbon film 32 meet at a common point, see fig 2, para 28).
LEE and KIM are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the layer geometry of KIM because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the layer geometry of KIM in order to improve electrical connections in the device (see KIM para 6).
Regarding claim 31, LEE discloses the vertical transistor of claim 1.
LEE fails to explicitly disclose a device, wherein a vertical surface of the oxide semiconductor layer extends in a straight, perpendicular line from the carbon thin film to the upper electrode.
KIM teaches a device, wherein a vertical surface of the oxide semiconductor layer extends in a straight, perpendicular line from the carbon thin film to the upper electrode (the semiconductor 44 has a vertical side surface that goes form the carbon film 32 to the upper electrode 48, see fig 2, para 28).
LEE and KIM are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the layer geometry of KIM because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the layer geometry of KIM in order to improve electrical connections in the device (see KIM para 6).
Regarding claim 32, LEE discloses the vertical transistor of claim 1.
LEE fails to explicitly disclose a device, wherein an upper surface of the lower electrode directly contacts a lower surface of the carbon thin film, and an upper surface of the oxide semiconductor layer directly contacts a lower surface of the upper electrode.
KIM teaches a device, wherein an upper surface of the lower electrode directly contacts a lower surface of the carbon thin film, and an upper surface of the oxide semiconductor layer directly contacts a lower surface of the upper electrode (the upper surface of the lower electrode 16 directly contacts the carbon thin film 32, and an upper surface of the semiconductor 44directly contacts a lower surface of upper electrode 48, see fig 2, para 28).
LEE and KIM are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the layer geometry of KIM because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the layer geometry of KIM in order to improve electrical connections in the device (see KIM para 6).
Response to Arguments
Applicant's arguments filed 3/23/22026 have been fully considered but they are not persuasive.
Regarding claim 1, the applicant argues that LEE does not disclose the claimed invention since LEE does not disclose “the lower electrode, the carbon thin film, the oxide semiconductor layer, and the upper electrode are arranged in a direction perpendicular to the substrate” because the oxide semiconductor of LEE (340, see fig 8) is conformal to a side surface of 320 and does not have vertical side surfaces. The argument is not persuasive because this is not required by the claim. The claim requires only that the elements be arranged in a direction perpendicular to the substrate. To arrange is to place them in a particular position (definition taken from Collins Dictionary on 5/16/2026). LEE discloses a device in fig 8 which has a lower electrode (SE3, see para 125), a carbon thin film (graphene 360, see fig 8, para 157), an oxide semiconductor layer (340, see para 136) and an upper electrode (330, see para 125) all of which are in particular positions in a direction (above the substrate, see fig 8) which is perpendicular to a top surface of the substrate (310, see para 126). This is all the claim requires. It is true that LEE does not disclose any of these layers which have vertical side surfaces, but this limitation is not present in the claim. For at least these reasons, and those given in the rejection above, LEE discloses every element of claim 1.
Regarding claim 1, the applicant argues that YANAZAKI does not disclose the claimed invention since LEE does not disclose “the lower electrode, the carbon thin film, the oxide semiconductor layer, and the upper electrode are arranged in a direction perpendicular to the substrate” because the films 121 etc. of YAMAZAKI are arranged in a serpentine manner. The argument is not persuasive because there is no requirement in the claim that the films not be serpentine, or that they have singe, vertical side surfaces as the argument implies. The claim requires only that the elements be arranged in a direction perpendicular to the substrate. To arrange is to place them in a particular position (definition taken from Collins Dictionary on 5/16/2026). YAMAZAKI discloses a device in fig 1-7 a device which has a lower electrode (122, see para 250), a carbon thin film (graphene 125, para 232-234), an oxide semiconductor layer (127, see para 170) and an upper electrode (BL, see para 369) all of which are in particular positions in a direction (above the substrate, see fig 1-7) which is perpendicular to a top surface of the substrate (121, see para 137). This is all the claim requires. It is true that YAMAZAKI does not disclose any of these layers which have only a single vertical side surface, or that all these layers be aligned along a line perpendicular to the substrate, but these limitations are not present in the claim. For at least these reasons, and those given in the rejection above, YAMAZAKI discloses every element of claim 1.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
Prosecution Insights