DETAILED ACTION
This Office Action is in response to Applicant’s application 18/457,883 filed on August 29, 2023 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on August 29, 2023 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on August 29, 2023 and October 8, 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. 2019/0096808 (Tsutsumi).
Regarding claim 1 Tsutsumi discloses at annotated Figure 5B, 5F and 10 a three-dimensional memory device, comprising:
an alternating stack of insulating layers, 32 [0053], and electrically conductive layers, 46 [0109];
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a memory opening, as annotated and shown in Figure 5B as 49 [0094] vertically extending through the alternating stack, as shown;
a memory opening fill structure, 55 [0093] / 602 [0087], located in memory opening, as shown, and comprising a vertical stack of memory elements, as annotated in Figure 5F, located at levels of the electrically conductive layers, where 42 is replaced by conductive layer 46, and a
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vertical semiconductor channel, 602 [0087];
a layer contact via structure, as annotated, contacting a first electrically conductive layer, as annotated and shown, within a first subset of the electrically conductive layers, as annotated, and vertically extending through a second subset of the electrically conductive layers, as shown and annotated, that overlies the first subset, as shown; and
a first-type support pillar structure, 20 [0094], located under a bottom surface of the layer contact via structure, as shown.
Allowable Subject Matter
Claims 2-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2 the prior art does not disclose the device of claim 1, wherein: the first-type support pillar structure contacts a center portion of the bottom surface of the layer contact via structure; and a bottom surface of the layer contact via structure contacts an annular horizontal surface segment of the first electrically conductive layer.
Regarding claim 3 the prior art does not disclose the device of claim 1, further comprising second-type support pillar structures laterally surrounding the layer contact via structure and having a greater vertical extent than the first-type support pillar structure.
Claims 4-10 depend directly or indirectly on claim 3 and are allowable on that basis.
Regarding claim 11 the prior art does not disclose the device of claim 1, wherein: the first-type support pillar structure comprises a top surface containing a divot therein; and the divot is filled with an insulating divot fill material portion that contacts a center potion of a bottom surface of the layer contact via structure.
Regarding claim 12 the prior art does not disclose the device of claim 1, wherein the first-type support pillar structure consists essentially of an insulating material, and comprises a first-type dielectric pillar structure.
Regarding claim 13 the prior art does not disclose the device of claim 1, wherein: the memory opening fill structure further comprises a first blocking dielectric layer and a first dielectric core laterally surrounded by the vertical semiconductor channel; and the first-type support pillar structure comprises a second blocking dielectric layer having a same material composition as the first blocking dielectric layer and second dielectric core laterally surrounded by and contacting the second blocking dielectric layer.
Regarding claim 14 the prior art does not disclose the device of claim 1, wherein: the first-type support pillar structure comprises a dummy semiconductor channel, a second dielectric core laterally surrounded by and contacting the dummy semiconductor channel, a dummy drain region, and a dummy memory film comprising a dummy blocking dielectric layer, a dummy memory material layer, and a dummy tunneling dielectric layer.
Regarding claim 15 the prior art does not disclose the device of claim 1, wherein: the bottom surface of the layer contact via structure comprises a center portion and a peripheral portion located below the center portion; the first-type support pillar structure contacts the center portion of the bottom surface of the layer contact via structure; a top surface of the first-type support pillar structure is located above the peripheral portion of the bottom surface of the layer contact via structure; and a tubular insulating spacer surrounds a top portion of the first-type support pillar structure.
Claims 16-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 16 the prior art fails to disclose a method of forming a memory device, comprising: forming an alternating stack of insulating layers and sacrificial material layers over a substrate; forming support pillar structures through the alternating stack, wherein the support pillar structures comprise a first-type support pillar structure and second-type support pillar structures that laterally surround the first-type support pillar structure; forming a memory opening through the alternating stack; forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a vertical stack of memory elements located at levels of the sacrificial material layers and a vertical semiconductor channel; forming a contact via cavity by vertically recessing the first-type support pillar structure and a neighboring portion of the alternating stack, wherein a remaining portion of the first-type support pillar structure is located below the contact via cavity; replacing the sacrificial material layers with electrically conductive layers; and forming a layer contact via in the contact via cavity on a first electrically conductive layer of the electrically conductive layers.
Claims 17-20 depend directly or indirectly on claim 16 and are allowable on that basis.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893