DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The examiner acknowledges amendments to claims 1-3, 5, 11-14, and 20 in the reply dated 30 July 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10, and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20240215273 A1, hereinafter “Yang”), in view of Kim et al (US 20210272631 A1, hereinafter “Kim”).
Regarding Claim 1 - Yang discloses a semiconductor device comprising: a first substrate having a first surface and a second surface facing opposite the first surface (3006 [0521] and Fig. 30G); a stack structure disposed on the first surface of the first substrate (3092 [0520] and Fig. 30G), and including a plurality of interlayer insulating layers (308 [0139] and Fig. 3A) and a plurality of horizontal wiring layers (306 [0139] and Fig. 3A) that are alternately stacked (Fig. 3A), and a plurality of channel structures that pass through the plurality of interlayer insulating layers and the plurality of horizontal wiring layers (320 [0140] and Fig. 3A); a plurality of upper transistors on the second surface of the first substrate (3061 and 3063 [0524] and Fig. 30G); and a logic structure disposed on the stack structure, and including a plurality of lower transistors (3081 and 3083 [0527] and Fig. 30G).
Yang fails to disclose a common source line disposed at substantially the same vertical level as the first substrate on the stack structure, wherein the common source line is disposed to overlap the first substrate in a horizontal direction and is connected to the plurality of channel structures.
However, Kim discloses a common source line disposed at substantially the same vertical level as the first substrate on the stack structure (e.g. CSL on same level as PTG3 in Kim Fig. 5), wherein the common source line is disposed to overlap the first substrate in a horizontal direction and is connected to the plurality of channel structures (Kim [0034] and Figs. 2 and 5).
Kim discloses an analogous 3D memory structure to Yang. Kim teaches placing a common source line (CSL) on the same level as pass transistors in the substrate, overlapping the first substrate in a horizontal direction, for the benefit of reduced quantity and size of pass transistors (Kim [0016]), allowing stacking of a plurality of sub-cell arrays (CAn) (Kim [0041]), leading to higher-integration semiconductor devices (Kim [0003]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Yang and Kim to place a common source line on the same level as pass transistors in the substrate, overlapping the first substrate in a horizontal direction, for the benefit of reduced quantity and size of pass transistors, allowing stacking of a plurality of sub-cell arrays, leading to higher-integration semiconductor devices.
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Regarding Claim 2 - Yang modified by Kim discloses all the limitations of claim 1.
The combination of Yang and Kim further discloses the plurality of upper transistors include an upper pass transistor (Peripheral circuits can include any circuits to facilitate memory cell operation, Yang [0122], and apply pass voltage Yang [0177]), which is connected to a corresponding horizontal wiring layer (word lines, Yang [0177]), and the plurality of lower transistors include a lower pass transistor (Peripheral circuits can include any circuits to facilitate memory cell operation, Yang [0122], and apply pass voltage, Yang [0177]), which is connected to a different corresponding horizontal wiring layer (word lines, Yang [0177]).
Regarding Claim 3 - Yang modified by Kim discloses all the limitations of claim 2.
The combination of Yang and Kim further discloses the stack structure further includes: first and second contact plugs (CP1 and CP2, annotated Yang Fig. 30G), each of which is connected to a corresponding one among the plurality of horizontal wiring layers (Yang Fig. 30G); and a first through electrode passing through the stack structure (TSV1, annotated Yang Fig. 30G), wherein the upper pass transistor is connected to the first contact plug via the first through electrode (Annotated Yang Fig. 30G), and wherein the lower pass transistor is connected to the second contact plug (Annotated Yang Fig. 30G).
Regarding Claim 10 - Yang modified by Kim discloses all the limitations of claim 1.
The combination of Yang and Kim further discloses at least one among the plurality of upper transistors and the plurality of lower transistors includes a plurality of page buffer transistors (Yang [0122], [0524], [0527]), which are connected to the plurality of channel structures (Yang Fig. 30G).
Regarding Claim 13 - Yang discloses a semiconductor device comprising: a first substrate having a first surface and a second surface that faces opposite the first surface (3006 [0521] and Fig. 30G); a stack structure disposed on the first surface of the first substrate (3092 [0520] and Fig. 30G) and including a plurality of interlayer insulating layers (308 [0139] and Fig. 3A) and a plurality of horizontal wiring layers (306 [0139] and Fig. 3A) that are alternately stacked (Fig. 3A), and a plurality of channel structures that pass through the plurality of interlayer insulating layers and the plurality of horizontal wiring layers (320 [0140] and Fig. 3A), the stack structure having a cell area and a connection area that is continuous to the cell area (Annotated Fig. 30G), with the plurality of channel structures disposed in the cell area (Fig. 30G); a plurality of upper transistors on the second surface of the first substrate (3061 and 3063 [0524] and Fig. 30G); and a logic structure bonded onto the stack structure, and including a plurality of lower transistors (3081 and 3083 [0527] and Fig. 30G).
Yang fails to disclose a common source line disposed at substantially the same vertical level as the first substrate on the stack structure, wherein the common source line is disposed to overlap the first substrate in a horizontal direction and is connected to the plurality of channel structures.
However, Kim discloses a common source line disposed at substantially the same vertical level as the first substrate on the stack structure (e.g. CSL on same level as PTG3 in Kim Fig. 5), wherein the common source line is disposed to overlap the first substrate in a horizontal direction and is connected to the plurality of channel structures (Kim [0034] and Figs. 2 and 5).
Kim discloses an analogous 3D memory structure to Yang. Kim teaches placing a common source line (CSL) on the same level as pass transistors in the substrate, overlapping the first substrate in a horizontal direction, for the benefit of reduced quantity and size of pass transistors (Kim [0016]), allowing stacking of a plurality of sub-cell arrays (CAn) (Kim [0041]), leading to higher-integration semiconductor devices (Kim [0003]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Yang and Kim to place a common source line on the same level as pass transistors in the substrate, overlapping the first substrate in a horizontal direction, for the benefit of reduced quantity and size of pass transistors, allowing stacking of a plurality of sub-cell arrays, leading to higher-integration semiconductor devices.
Regarding Claim 14 - Yang modified by Kim discloses all the limitations of claim 13.
The combination of Yang and Kim further discloses the plurality of upper transistors are aligned at an upper part of the connection area (interpreted as over the connection area, Yang Fig. 30G).
Regarding Claim 15 - Yang modified by Kim discloses all the limitations of claim 13.
The combination of Yang and Kim further discloses the common source line is aligned at an upper part of the cell area (Common source line vertically aligned with cell area, Kim Fig. 5).
Regarding Claim 16 - Yang modified by Kim discloses all the limitations of claim 13.
The combination of Yang and Kim further discloses a lower surface of the common source line forms substantially the same plane as the first surface (same as interface of stack structure and transistor substrate of Yang Fig. 30G), and an upper surface of the common source line forms substantially the same plane as the second surface (Second surface of substrate in Yang Fig. 30G).
Regarding Claim 17 - Yang modified by Kim discloses all the limitations of claim 13.
The combination of Yang and Kim further discloses each of the plurality of channel structures includes: a core layer (Core, annotated Yang Fig. 3A); a channel layer outside the core layer (320, Yang [0140] and Fig. 3A); a tunnel layer outside the channel layer (326, Yang [0140] and Fig. 3A); a charge trap layer outside the tunnel layer (324, Yang [0140] and Fig. 3A); and a blocking layer outside the charge trap layer (322, Yang [0140] and Fig. 3A), and wherein the channel layer directly contacts the common source line (Yang Fig. 3A).
Regarding Claim 20 - Yang discloses a semiconductor device comprising: a first substrate having a first surface and a second surface that faces opposite the first surface (3006 [0521] and Fig. 30G); a stack structure disposed on the first surface of the first substrate (3092 [0520] and Fig. 30G), and including a plurality of interlayer insulating layers (308 [0139] and Fig. 3A) and a plurality of horizontal wiring layers (306 [0139] and Fig. 3A) that are alternately stacked (Fig. 3A), and a plurality of channel structures that pass through the plurality of interlayer insulating layers and the plurality of horizontal wiring layers (320 [0140] and Fig. 3A); a plurality of upper transistors on the second surface of the first substrate (3061 and 3063 [0524] and Fig. 30G).
Yang fails to disclose a common source line disposed at substantially the same vertical level as the first substrate on the stack structure, wherein the common source line is disposed to overlap the first substrate in a horizontal direction and is connected to the plurality of channel structures.
However, Kim discloses a common source line disposed at substantially the same vertical level as the first substrate on the stack structure (e.g. CSL on same level as PTG3 in Kim Fig. 5), wherein the common source line is disposed to overlap the first substrate in a horizontal direction and is connected to the plurality of channel structures (Kim [0034] and Figs. 2 and 5).
Kim discloses an analogous 3D memory structure to Yang. Kim teaches placing a common source line (CSL) on the same level as pass transistors in the substrate, overlapping the first substrate in a horizontal direction, for the benefit of reduced quantity and size of pass transistors (Kim [0016]), allowing stacking of a plurality of sub-cell arrays (CAn) (Kim [0041]), leading to higher-integration semiconductor devices (Kim [0003]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Yang and Kim to place a common source line on the same level as pass transistors in the substrate, overlapping the first substrate in a horizontal direction, for the benefit of reduced quantity and size of pass transistors, allowing stacking of a plurality of sub-cell arrays, leading to higher-integration semiconductor devices.
Claims 4-8 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20240215273 A1, hereinafter “Yang”), in view of Kim et al (US 20210272631 A1, hereinafter “Kim”), and further in view of Choi (US 20240040791 A1, hereinafter “Choi”).
Regarding Claim 4 - Yang modified by Kim discloses all the limitations of claim 3.
The combination of Yang and Kim further discloses an interface between the logic structure and the stack structure (3007, Yang [0523] and Fig. 30G); and a plurality of upper pads between the plurality of intermediate interconnections and the interface, wherein the logic structure further includes a second substrate (3008, Yang [0523] and Fig. 30G), and wherein the logic structure is bonded onto the stack structure (Yang Fig. 30G).
Yang fails to disclose a plurality of intermediate interconnections between the stack structure and the interface, a plurality of lower interconnections between the second substrate and the interface, and a plurality of lower pads between the plurality of lower interconnections and the interface.
However, Choi discloses a plurality of intermediate interconnections between the stack structure and the interface (41 and 43 , Choi [0059] and Fig. 6A), a plurality of lower interconnections between the second substrate and the interface (31 and 33, Choi [0054] and Fig. 6A), and a plurality of lower pads between the plurality of lower interconnections and the interface (35, Choi [0054] and Fig. 6A)
Choi discloses a memory device comprising a logic and memory stack analogous to Yang. Choi teaches intermediate connections between the stack structure and second substrate, and connection pads at the interface, for the benefit of aligning connections to components to be connected (as seen by Interconnection Alignment in annotated Choi Fig. 6A). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Yang and Choi to use intermediate connections between the stack structure and second substrate, and connection pads at the interface, for the benefit of aligning connections to components to be connected.
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Regarding Claim 5 - Yang modified by Kim and Choi discloses all the limitations of claim 4.
The combination of Yang, Kim, and Choi further discloses each of the plurality of upper pads directly contacts a corresponding one among the plurality of lower pads (Choi Fig. 6A).
Regarding Claim 6 - Yang modified by Kim and Choi discloses all the limitations of claim 4.
The combination of Yang, Kim, and Choi further discloses the upper pass transistor is connected to the first contact plug via the first through electrode (Yang Fig. 30G) and the plurality of intermediate (41 and 43 , Choi [0059] and Fig. 6A).
Regarding Claim 7 - Yang modified by Kim and Choi discloses all the limitations of claim 4.
The combination of Yang, Kim, and Choi further discloses the upper pass transistor is connected to the first contact plug via the first through electrode, the plurality of intermediate interconnections, the plurality of upper pads, the plurality of lower pads and the plurality of lower interconnections (Yang Fig. 30G).
Regarding Claim 8 - Yang modified by Kim and Choi discloses all the limitations of claim 4.
The combination of Yang, Kim, and Choi further discloses the lower pass transistor is connected to the second contact plug via the plurality of lower interconnections, the plurality of lower pads, the plurality of upper pads and the plurality of intermediate interconnections (Yang Fig. 30G).
Regarding Claim 18 - Yang modified by Kim discloses all the limitations of claim 17.
Yang fails to disclose an uppermost end of the channel layer is at a level higher than a lowermost end of the common source line and the first surface.
However, Choi discloses an uppermost end of the channel layer (VSP, Choi [0080] and Fig. 7C) is at a level higher than a lowermost end of the common source line and the first surface (VT higher than bottom of SC1, Choi Fig. 7C).
Choi discloses a similar semiconductor memory device to Yang. Choi teaches exposing the top portion of the channel layer prior to common source line deposition for the benefit of direct contact between the two layers when the common source line is deposited without any additional steps (Choi [0120-0121]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Yang and Choi to expose the top portion of the channel layer prior to common source line deposition for the benefit of direct contact between two layers in the common source layer is deposited without any additional steps.
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Regarding Claim 19 - Yang modified by Kim discloses all the limitations of claim 17.
Yang fails to disclose an uppermost end of the core layer is at a level higher than a lowermost end of the common source line and the first surface.
However, Choi discloses an uppermost end of the core layer is at a level higher than a lowermost end of the common source line and the first surface (Top of VI higher than bottom of SC1, Choi Fig. 7C).
Choi discloses a similar semiconductor memory device to Yang. Choi teaches exposing the top portion of the channel layer with core layer inside prior to common source line deposition for the benefit of direct contact between the two layers when the common source line is deposited without any additional steps (Choi [0120-0121]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Yang and Choi to expose the top portion of the channel layer with core layer inside prior to common source line deposition for the benefit of direct contact between two layers in the common source layer is deposited without any additional steps.
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20240215273 A1, hereinafter “Yang”), in view of Kim et al (US 20210272631 A1, hereinafter “Kim”), and further in view of Kim et al (US 20220005820 A1, hereinafter “Kim2”).
Regarding Claim 9 - Yang modified by Kim discloses all the limitations of claim 2.
The combination of Yang and Kim further discloses a second through electrode passing through the stack structure (TSV2, annotated Yang Fig. 30G).
Yang fails to disclose at least one among the plurality of upper transistors and the plurality of lower transistors further includes a block switch transistor that is connected to the upper pass transistor and the lower pass transistor via the second through electrode.
However, Kim2 discloses upper and lower pass transistors in a row decoder (X-DEC) may further be connected to block switch transistors (Kim2 [0031] and Fig. 1).
Kim2 discloses a similar semiconductor memory device to Yang. Kim2 teaches a row decoder containing pass transistors may also contain a block switch for the benefit of selecting whole memory blocks (Kim2 [0031]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Yang and Kim2 to connect pass transistors to a block switch for the benefit of selecting whole memory blocks.
Regarding Claim 11 - Yang modified by Kim discloses all the limitations of claim 1.
The combination of Yang and Kim further discloses a third through electrode (a large number of TSVs can be formed, Yang [0128]) passing through the stack structure, wherein the plurality of upper transistors includes an upper page buffer transistor (e.g. 2863 (3063), Yang [0501] and Fig. 30G), and wherein the plurality of lower transistors includes a lower page buffer transistor (e.g. 2883 (3083), Yang [0505] and Fig. 30G).
Yang fails to disclose the page buffer transistors are each connected to a different channel structure.
However, Kim2 discloses the page buffer transistors are each connected to a different channel structure (Kim2 [0032] and Fig. 1).
Kim2 discloses a similar semiconductor memory device to Yang. Kim2 teaches coupling a page buffer to each channel structure (bit line) in order to read and write data from memory cells coupled to an active word line (Kim2 [0032]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Yang and Kim2 to connect a page buffer to each channel structure in order to read and write data from memory cells coupled to an active word line.
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Allowable Subject Matter
Claims 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 12 contains the following limitation not found in the prior art known to the examiner, alone or in combination: “...(T)he plurality of horizontal wiring layers include a first word line that is connected to the first and third contact plugs and a second word line that is connected to the second and fourth contact plugs, the plurality of upper transistors include a first upper pass transistor that is connected to the first contact plug and a second upper pass transistor that is connected to the third contact plug, and the plurality of lower transistors include a first lower pass transistor that is connected to the second contact plug and a second lower pass transistor that is connected to the fourth contact plug...”.
Relevant Prior Art:
Yang (US 20240215273 A1) teaches: “(A)n interconnect layer is formed above the multi gate DFM cells on the second semiconductor layer. The interconnect layer can include a first plurality of interconnects and one or more ILD layers.” ([0519]). Yang is silent with respect to word line connection routing.
Kim (US 20220005820 A1) teaches: “The row decoder may transfer an operating voltage provided from the peripheral circuit to word lines coupled to a memory block that is selected from among the memory blocks included in the memory cell array.” ([0031]). Yang is silent with respect to word line connection routing.
Fastow (US 20190043836 A1) teaches: “(W)afers are bonded with the top metal layers facing one another. ... does not include vias through the CMOS circuitry.” ([0039] and Fig. 2B) Fastow is silent with respect to word line connection routing.
Response to Arguments
Applicant submits that Yang does not disclose “a stack structure disposed on the first surface of the first substrate and including a plurality of interlayer insulating layers and a plurality of horizontal wiring layers that are alternately stacked, and a plurality of channel structures that pass through the plurality of interlayer insulating layers and the plurality of horizontal wiring layers”.
However, as referenced above, Yang Fig. 30G clearly shows the stack structure on a first side of the substrate 3006, whereas the pass transistors are on a second side.
Applicant’s other arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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