Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities:
Paragraphs 365, 391, & 440 all mention a "depression type" MOSFET, however this is not a known term in the art and likely means depletion type MOSFETs.
Paragraphs 112 and 120 both mention “substates 60 to 63” however these reference numbers are already assigned to electrodes in paragraph 111.
Appropriate correction is required.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 12 is objected to because of the following informalities: Line 2 of claim 12 reads "a seventh MOSFET of a depression type and an eighth MOSFET of a depression type ..." however "depression type" MOSFETs are not a known term in the art and likely means depletion type MOSFETs.
Appropriate correction is required.
Claim Interpretation
In claim 12 there is mention of "a seventh MOSFET of a depression type and an eighth MOSFET of a depression type ..." however “depression type” MOSFETs are not a known term in the art and for the purpose of examination all instances are being read as a “depletion type” MOSFET.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Imai (US Patent No. 11,212,779).
Regarding claim 1, Imai teaches (Fig. 1) a semiconductor device comprising a first insulating element (light emitting element 14A and light receiving element 20A; col. 2, lines 58-66) and a second insulating element (light emitting element 14B and light receiving element 20B; col. 2, lines 58-66) each controlled based on a control signal; a first control circuit configured to control selection (selection circuit 10; col. 2, lines 26-33) of one of the first insulating element and the second insulating element based on the control signal; a first switch element (switch 22A; col. 2, lines 39-45); a second switch element (switch 22B; col. 2, lines 39-45); a second control circuit configured to control the first switch element based on an output of the first insulating element and a third control circuit configured to control the second switch based on an output of the second insulating element (Col. 3 lines 36-41).
Regarding claim 2, Imai teaches the first switch element (Fig. 1, switch 22A) including a first MOSFET of an enhancement type (Fig. 2, MOSFET 220) and a second MOSFET of an enhancement type (Fig. 2, MOSFET 222), the second switch element (Fig. 1, switch 22B) includes a third MOSFET of an enhancement type (Fig. 2, MOSFET 220) and a fourth MOSFET of an enhancement type (Fig. 2, MOSFET 222), the second control circuit controls a first gate voltage and a first source voltage of the first MOSFET and a second gate voltage and a second source voltage of the second MOSFET based on the output of the first insulating element, and the third control circuit controls a third gate voltage and a third source voltage of the third MOSFET and a fourth gate voltage and a fourth source voltage of the fourth MSOFET based on the output of the second insulating element (Col. 3 lines 36-41).
Regarding claim 3, Imai teaches a source of the first MOSFET is coupled to a source of the second MOSFET (Fig. 1, switch 22A; Fig. 2, switch 22; col. 3, lines 52-56), and a source of the third MOSFET is coupled to a source of the fourth MOSFET (Fig 1, switch 22B; Fig. 2, switch 22; col. 3, lines 52-56).
Regarding claim 5, Imai teaches (Fig. 1) the first insulating element including a first light emitting element (light emitting element 14A) and a first light receiving element (light receiving element 20A) and the second insulating element includes a second light emitting element (light emitting element 14B) and a second light receiving element (light receiving element 20B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of Toshiba Electronic Devices & Storage Corporation’s document titled "How to replace mechanical relays with photorelays" hereinafter referred to as Toshiba.
Regarding claim 4, Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 4 is dependent. However, Imai does not teach the first control circuit including a first transistor having a gate to which the control signal is input, a source to which a power supply voltage is applied, and a drain coupled to a first node; and a second transistor having a gate to which the control signal is input, a drain coupled to the first node, and a source to which a ground voltage is applied, and one of the first insulating element and the second insulating element being selected based on a voltage of the first node.
Toshiba teaches (Fig. 4.4.5; pg. 13) the first control circuit including a first transistor having a gate to which the control signal is input, a source to which a power supply voltage is applied, and a drain coupled to a first node; and a second transistor having a gate to which the control signal is input, a drain coupled to the first node, and a source to which a ground voltage is applied.
Imai and Toshiba are analogous art as they are in the same field of endeavor of photo relays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Imai’s control circuit to incorporate the teachings of Toshiba to use a CMOS drive circuit to control the first and second light emitting elements of Imai due to the excellent noise immunity of the CMOS drive circuit and because the CMOS drive circuit is a typical drive circuit for a photo relay, as recognized by Toshiba.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of Toshiba and in further view of the article by Zhang et al. titled “Research on Simulation Design of MOS Driver for Micro-LED” hereinafter referred to as Zhang et al.
Regarding claim 6, Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 6 is dependent. However, Imai does not teach the first control circuit including a first transistor having a gate to which the control signal is input, a source to which a power supply voltage is applied, and a drain coupled to a first node; and a second transistor having a gate to which the control signal is input, a drain coupled to the first node, and a source to which a ground voltage is applied, and an anode of the first light emitting element coupled to the source of the first transistor, a cathode of the first light emitting element coupled to the first node, an anode of the second light emitting element coupled to the first node, and a cathode of the second light emitting element coupled to the source of the second transistor.
Toshiba teaches (Fig. 4.4.5; pg. 13) the first control circuit including a first transistor having a gate to which the control signal is input, a source to which a power supply voltage is applied, and a drain coupled to a first node; and a second transistor having a gate to which the control signal is input, a drain coupled to the first node, and a source to which a ground voltage is applied, and an anode of the light emitting element being coupled to the source of the first transistor, and a cathode of the light emitting element being couple to the first node.
Zhang et al. teaches (Fig. 9c) the first control circuit including a first transistor having a gate to which the control signal is input, a source to which a power supply voltage is applied, and a drain coupled to a first node; and a second transistor having a gate to which the control signal is input, a drain coupled to the first node, and a source to which a ground voltage is applied, and an anode of the light emitting element being coupled to the first node, and a cathode of the light emitting element being coupled to the source of the second transistor.
Imai and Toshiba and Zhang et al. are all analogous art as they are in the same field of endeavor of optoelectronics. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Imai’s control circuit to incorporate the teachings of Toshiba and Zhang et al. to use a CMOS drive circuit to control the first and second light emitting elements of Imai due to the excellent noise immunity of the CMOS drive circuit and because the CMOS drive circuit is a typical drive circuit for a photo relay, as recognized by Toshiba. Also, the size of CMOS devices being easily reduced and the low manufacturing costs, as recognized by Zhang et al.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of Fujihara et al. (Pub. No. US20210247567A1).
Regarding claim 7, Imai teaches all the elements of claim 5, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 7 is dependent. Imai does not teach the semiconductor device further comprising a substrate, wherein the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET are provided above the substrate, the first light receiving element and the second light receiving element are provided above the substrate, the first light emitting element is provided above the first light receiving element, the second light emitting element is provided above the second light receiving element, a partial upper surface of the first light receiving element and the first light emitting element are covered with a first sealing member, and a partial upper surface of the second light receiving element and the second light emitting element are covered with a second sealing member.
Fujihara et al. teaches the semiconductor device further comprising a substrate, wherein the MOSFETs are provided above the substrate (Figs. 7A-7C, substrate 110, MOSFET 13 and 14; ¶63), the light receiving element is provided above the substrate (Figs. 7A-7C, light receiving element 11, substate 110; ¶63), the light emitting element is provided above the light receiving element (Fig. 1, light receiving element 11, light emitting element 12; ¶12, lines 1-6), and a partial upper surface of the light receiving element and the light emitting element are covered with a sealing member (Figs. 2A-2C, light receiving element 11, light emitting element 12, light transmitting member 43; ¶20, lines 9-19).
Imai and Fujihara et al. are analogous art as they are in the same field of endeavor of photo relays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Imai to incorporate the teachings of Fujihara et al. to have the MOSFETs and insulating elements above the substrate, the light emitting elements above the light receiving elements, and to have the partial upper surface of the light receiving elements and the light emitting elements covered with a resin all for the purpose of improving photoelectric effects, and protecting the adhesive layer between the light emitting and light receiving elements.
Regarding claim 8, Imai teaches all the elements of claim 5, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 8 is dependent. Imai does not teach the semiconductor device further comprising a substrate, wherein the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET are provided above the substrate, the first light receiving element is provided on the first MOSFET and the second MOSFET, the second light receiving element is provided on the third MOSFET and the fourth MOSFET, the first light emitting element is provided above the first light receiving element, and the second light emitting element is provided above the second light receiving element.
Fujihara et al. teaches the semiconductor device further comprising a substrate, wherein the MOSFETs are provided above the substrate (Figs. 7A-7C, substrate 110, MOSFET 13 and 14; ¶63), the light receiving element is provided on the MOSFETs (Figs. 6A-6C, light receiving element 11, MOSFET 16 and 17; ¶59 & 60), and the light emitting element is provided above the light receiving element (Fig. 1, light receiving element 11, light emitting element 12; ¶12, lines 1-6).
Imai and Fujihara et al. are analogous art as they are in the same field of endeavor of photo relays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Imai to incorporate the teachings of Fujihara et al. to have the light receiving elements provided on the MOSFETs for the purpose of increasing the size of the switching elements and increasing the high frequency current flowing through the device without increasing the size of the entire device, as recognized by Fujihara et al.
Regarding claim 9, Imai teaches all the elements of claim 5, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 9 is dependent. Imai does not teach the semiconductor device further comprising a substrate, wherein the first MOSFET and the second MOSFET are integrally provided above the substrate, the third MOSFET and the fourth MOSFET are integrally provided above the substrate, the first light receiving element is provided on the first MOSFET and the second MOSFET, the second light receiving element is provided on the third MOSFET and the fourth MOSFET, the first light emitting element is provided above the first light receiving element, and the second light emitting element is provided above the second light receiving element.
Fujihara et al. teaches the semiconductor device further comprising a substrate, wherein the MOSFETs are integrally provided above the substrate (Figs. 5A-5C, MOSFET 15; Figs. 7A-7C, substrate 110; ¶47-48 & 63), the light receiving element is provided on the MOSFETs (Figs. 6A-6C, light receiving element 11, MOSFET 16 and 17; ¶59 & 60), and the light emitting element is provided above the light receiving element (Fig. 1, light receiving element 11, light emitting element 12; ¶12, lines 1-6).
Imai and Fujihara et al. are analogous art as they are in the same field of endeavor of photo relays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Imai to incorporate the teachings of Fujihara et al. to have the MOSFETs integrally provided above the substrate and to have the light receiving elements provided on the MOSFETs for the purpose increasing the size of the switching elements, increasing the high frequency current flowing through the device without increasing the size of the entire device, and reducing the parasitic capacitance between the source and drain of the MOSFETs, as recognized by Fujihara et al.
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of Hesse et al. (US Patent No. 10,181,786).
Regarding claim 10, Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 10 is dependent. Imai does not teach the first control circuit including a first circuit configured to cause, based on the control signal, one of the first insulating element and the second insulating element to operate at a timing different from a timing of a remaining one.
Hesse et al. teaches the first control circuit including a first circuit configured to cause, based on the control signal, one of the first insulating element and the second insulating element to operate at a timing different from a timing of a remaining one (Fig. 1 & 4, Control circuit 104, high-side FET 106, low-side FET 110, high side adjustable delay circuit 438, high-side fixed delay circuit 440, low-side adjustable delay circuit 452, low-side fixed delay circuit 454; Col. 4, line 61 – Col. 5, line 7; Col. 9, line 3 – Col. 10, line 21).
Imai and Hesse et al. are analogous art as they are in the same field of endeavor of operating MOSFET switches. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Imai to incorporate the teachings of Hesse et al. to use the control circuit of Hesse et al. to operate the light emitting elements of Imai for the purpose of preventing cross conduction or “shoot-through” which can damage the device, as recognized by Hesse et al.
Regarding claim 11, Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 11 is dependent. Imai does not teach the first control circuit including a first circuit configured to cause, based on the control signal, one of the first insulating element and the second insulating element to operate at a timing different from a timing of a remaining one. Imai also does not teach the first control circuit further including a second circuit configured to drive the first insulating element based on a first voltage, and a third circuit configured to drive the second insulating element based on a second voltage, and the first circuit supplies the first voltage to the second circuit at a first time based on the control signal, and supplies the second voltage to the third circuit at a second time different from the first time based on the control signal.
Hesse et al. teaches the first control circuit including a first circuit configured to cause, based on the control signal, one of the first insulating element and the second insulating element to operate at a timing different from a timing of a remaining one (Fig. 1 & 4, Control circuit 104, high-side FET 106, low-side FET 110, high side adjustable delay circuit 438, high-side fixed delay circuit 440, low-side adjustable delay circuit 452, low-side fixed delay circuit 454; Col. 4, line 61 – Col. 5, line 7; Col. 9, line 3 – Col. 10, line 21). Hesse et al. also teaches the first control circuit further including a second circuit configured to drive the first insulating element based on a first voltage (Fig. 1, high-side drive circuit 108; Col. 9, lines 38-54), and a third circuit configured to drive the second insulating element based on a second voltage (Fig.1, low-side drive circuit 110), and the first circuit supplies the first voltage to the second circuit at a first time based on the control signal, and supplies the second voltage to the third circuit at a second time different from the first time based on the control signal (Col. 10, line 67 – Col. 11, line 3).
Imai and Hesse et al. are analogous art as they are in the same field of endeavor of operating MOSFET switches. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Imai to incorporate the teachings of Hesse et al. to use the control and driver circuits of Hesse et al. to operate the light emitting elements of Imai for the purpose of preventing cross conduction or “shoot-through” which can damage the device, as recognized by Hesse et al.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of Sunada et al. (Patent No. JP2016063298A).
Regarding claim 12, Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 12 is dependent. Imai also teaches the first switch element including a fifth MOSFET of an enhancement type and a sixth MOSFET of an enhancement type (Fig. 1, switch 22A; Fig. 2, MOSFETs 220 & 222, switch 22; Col. 3, lines 52-56), the second control circuit controlling a fifth gate voltage and a fifth source voltage of the fifth MOSFET and a sixth gate voltage and a sixth source voltage of the sixth MOSFET based on the output of the first insulating element, and the third control circuit controlling a seventh gate voltage and a seventh source voltage of the seventh MOSFET and an eighth gate voltage and an eighth source voltage of the eighth MOSFET based on the output of the second insulating element (Col. 3, lines 36-41). However, Imai does not teach the second switch element including a seventh MOSFET of a depletion type and an eighth MOSFET of a depletion type.
Sunada et al. teaches the second switch element including a seventh MOSFET of a depletion type and an eighth MOSFET of a depletion type (Fig. 1, second depletion-type MOSFET 3, second MOSFET 3A & 3B; ¶21-22).
Imai and Sunada et al. are analogous art as they are in the same field of endeavor of photo relays. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Imai to incorporate the teachings of Sunada et al. to have the second switch element have depletion type MOSFETs for the purpose of improving the break-before-make operation of the device, as recognized by Sunada et al.
Regarding claim 13, Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 13 is dependent. Imai also teaches the first switch element including a fifth MOSFET of an enhancement type and a sixth MOSFET of an enhancement type (Fig. 1, switch 22A; Fig. 2, MOSFETs 220 & 222, switch 22; Col. 3, lines 52-56), the second control circuit controlling a fifth gate voltage and a fifth source voltage of the fifth MOSFET and a sixth gate voltage and a sixth source voltage of the sixth MOSFET based on the output of the first insulating element, and the third control circuit controlling a seventh gate voltage and a seventh source voltage of the seventh MOSFET and an eighth gate voltage and an eighth source voltage of the eighth MOSFET based on the output of the second insulating element (Col. 3, lines 36-41). However, Imai does not teach the second switch element including a seventh MOSFET of a depletion type and an eighth MOSFET of a depletion type, a source of the fifth MOSFET being coupled to a source of the sixth MOSFET, and a source of the seventh MOSFET being coupled to a source of the eighth MOSFET.
Sunada et al. teaches (Fig. 1) the second switch element including a seventh MOSFET of a depletion type and an eighth MOSFET of a depletion type (second depletion-type MOSFET 3, second MOSFET 3A & 3B; ¶21-22), a source of the fifth MOSFET being coupled to a source of the sixth MOSFET (First enhancement-type MOSFET 1, first MOSFET 1A & 1B; ¶25), and a source of the seventh MOSFET being coupled to a source of the eighth MOSFET (Second depletion-type MOSFET 3, second MOSFET 3A & 3B; ¶34).
Imai and Sunada et al. are analogous art as they are in the same field of endeavor of photo relays. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Imai to incorporate the teachings of Sunada et al. to have the second switch element have depletion type MOSFETs and to have the sources of the MOSFETs in the switch elements connected for the purpose of having a bidirectional switch and improving the break-before-make operation of the device, as recognized by Sunada et al.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of Hesse et al. and Sunada et al.
Regarding claim 14, Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 14 is dependent. Imai also teaches the first switch element including a fifth MOSFET of an enhancement type and a sixth MOSFET of an enhancement type (Fig. 1, switch 22A; Fig. 2, MOSFETs 220 & 222, switch 22; Col. 3, lines 52-56), the second control circuit controlling a fifth gate voltage and a fifth source voltage of the fifth MOSFET and a sixth gate voltage and a sixth source voltage of the sixth MOSFET based on the output of the first insulating element, and the third control circuit controlling a seventh gate voltage and a seventh source voltage of the seventh MOSFET and an eighth gate voltage and an eighth source voltage of the eighth MOSFET based on the output of the second insulating element (Col. 3, lines 36-41). However, Imai does not teach the second switch element including a seventh MOSFET of a depletion type and an eighth MOSFET of a depletion type, a source of the fifth MOSFET being coupled to a source of the sixth MOSFET, and a source of the seventh MOSFET being coupled to a source of the eighth MOSFET. Imai also does not teach the first control circuit including a first circuit configured to cause, based on the control signal, one of the first insulating element and the second insulating element to operate at a timing different from a timing of a remaining one.
Sunada et al. teaches (Fig. 1) the second switch element including a seventh MOSFET of a depletion type and an eighth MOSFET of a depletion type (second depletion-type MOSFET 3, second MOSFET 3A & 3B; ¶21-22), a source of the fifth MOSFET being coupled to a source of the sixth MOSFET (First enhancement-type MOSFET 1, first MOSFET 1A & 1B; ¶25), and a source of the seventh MOSFET being coupled to a source of the eighth MOSFET (Second depletion-type MOSFET 3, second MOSFET 3A & 3B; ¶34).
Hesse et al. teaches the first control circuit including a first circuit configured to cause, based on the control signal, one of the first insulating element and the second insulating element to operate at a timing different from a timing of a remaining one (Fig. 1 & 4, Control circuit 104, high-side FET 106, low-side FET 110, high side adjustable delay circuit 438, high-side fixed delay circuit 440, low-side adjustable delay circuit 452, low-side fixed delay circuit 454; Col. 4, line 61 – Col. 5, line 7; Col. 9, line 3 – Col. 10, line 21).
Imai, Sunada et al., and Hesse et al. are analogous are as they are all in the same field of endeavor of operating MOSFET switches. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Imai to incorporate the teachings of Hesse et al. and Sunada et al. to have the second switch element have depletion type MOSFETs and to have the sources of the MOSFETs in the switch elements connected for the purpose of having a bidirectional switch and improving the break-before-make operation of the device, as recognized by Sunada et al. Also to use the control circuit of Hesse et al. to operate the light emitting elements of Imai for the purpose of preventing cross conduction or “shoot-through” which can damage the device, as recognized by Hesse et al.
Regarding claim 15, Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 15 is dependent. Imai also teaches the first switch element including a fifth MOSFET of an enhancement type and a sixth MOSFET of an enhancement type (Fig. 1, switch 22A; Fig. 2, MOSFETs 220 & 222, switch 22; Col. 3, lines 52-56), the second control circuit controlling a fifth gate voltage and a fifth source voltage of the fifth MOSFET and a sixth gate voltage and a sixth source voltage of the sixth MOSFET based on the output of the first insulating element, and the third control circuit controlling a seventh gate voltage and a seventh source voltage of the seventh MOSFET and an eighth gate voltage and an eighth source voltage of the eighth MOSFET based on the output of the second insulating element (Col. 3, lines 36-41). However, Imai does not teach the second switch element including a seventh MOSFET of a depletion type and an eighth MOSFET of a depletion type, a source of the fifth MOSFET being coupled to a source of the sixth MOSFET, and a source of the seventh MOSFET being coupled to a source of the eighth MOSFET. Imai also does not teach the first control circuit including a first circuit configured to cause, based on the control signal, one of the first insulating element and the second insulating element to operate at a timing different from a timing of a remaining one. Imai also does not teach the first control circuit further including a second circuit configured to drive the first insulating element based on a first voltage, and a third circuit configured to drive the second insulating element based on a second voltage, and the first circuit supplies the first voltage to the second circuit at a first time based on the control signal, and supplies the second voltage to the third circuit at a second time different from the first time based on the control signal.
Sunada et al. teaches (Fig. 1) the second switch element including a seventh MOSFET of a depletion type and an eighth MOSFET of a depletion type (second depletion-type MOSFET 3, second MOSFET 3A & 3B; ¶21-22), a source of the fifth MOSFET being coupled to a source of the sixth MOSFET (First enhancement-type MOSFET 1, first MOSFET 1A & 1B; ¶25), and a source of the seventh MOSFET being coupled to a source of the eighth MOSFET (Second depletion-type MOSFET 3, second MOSFET 3A & 3B; ¶34).
Hesse et al. teaches the first control circuit including a first circuit configured to cause, based on the control signal, one of the first insulating element and the second insulating element to operate at a timing different from a timing of a remaining one (Fig. 1 & 4, Control circuit 104, high-side FET 106, low-side FET 110, high side adjustable delay circuit 438, high-side fixed delay circuit 440, low-side adjustable delay circuit 452, low-side fixed delay circuit 454; Col. 4, line 61 – Col. 5, line 7; Col. 9, line 3 – Col. 10, line 21). Hesse et al. also teaches the first control circuit further including a second circuit configured to drive the first insulating element based on a first voltage (Fig. 1, high-side drive circuit 108; Col. 9, lines 38-54), and a third circuit configured to drive the second insulating element based on a second voltage (Fig.1, low-side drive circuit 110), and the first circuit supplies the first voltage to the second circuit at a first time based on the control signal, and supplies the second voltage to the third circuit at a second time different from the first time based on the control signal (Col. 10, line 67 – Col. 11, line 3).
Imai, Sunada et al., and Hesse et al. are analogous are as they are all in the same field of endeavor of operating MOSFET switches. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Imai to incorporate the teachings of Hesse et al. and Sunada et al. to have the second switch element have depletion type MOSFETs and to have the sources of the MOSFETs in the switch elements connected for the purpose of having a bidirectional switch and improving the break-before-make operation of the device, as recognized by Sunada et al. Also to use the control and driver circuits of Hesse et al. to operate the light emitting elements of Imai for the purpose of preventing cross conduction or “shoot-through” which can damage the device, as recognized by Hesse et al.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of Yamagishi (US Patent No. 6,806,482).
Regarding claim 16, Imai teaches all the elements of claim 2, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 16 is dependent. Imai does not teach the drain of the first MOSFET being coupled to a drain of the second MOSFET and a drain of the third MOSFET being coupled to a drain of the fourth MOSFET.
Yamagishi teaches the drain of the first MOSFET being coupled to a drain of the second MOSFET (Figs. 3 & 9, Switch 20, transistors 21a & 21b, circuit node 15; Col. 4, lines 36-41).
Imai and Yamagishi are analogous art as they are in the same field of endeavor of photo relays. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Imai to incorporate the teachings of Yamagishi to connect the drains of the MOSFETs in the switch elements for the purpose of making the switches bidirectional, as recognized by Yamagishi et al.
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of Ushiyama et al. (Patent No. JP202018742A).
Regarding claim 17, Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 17 is dependent. Imai does not teach the first insulating element and the second insulating element including two coils.
Ushiyama et al. teaches the insulating element including two coils (Fig. 4, Magnetic coupling type isolator IC23, input unit 24, and output unit 25; ¶59).
Imai and Ushiyama are analogous art as they are in the same field of semiconductor relays. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Imai to incorporate the teachings of Ushiyama to have the first and second insulating elements include two coils for the purpose of using magnetic coupling to insulate the primary side circuit and secondary side circuit, as recognized by Ushiyama.
Regarding claim 18, Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 18 is dependent. Imai does not teach the first insulating element and the second insulating element including a capacitance element.
Ushiyama teaches the insulating element being a capacitance element (Fig. 5, Capacitively coupled isolator IC26, input unit 27, and output unit 28; ¶59-60).
Imai and Ushiyama are analogous art as they are in the same field of semiconductor relays. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Imai to incorporate the teachings of Ushiyama to have the first and second insulating elements include a capacitance element for the purpose of using capacitively coupled elements to insulate the primary side circuit and secondary side circuit, as recognized by Ushiyama.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of Choe et al. (Pub. No. US20170256507A1).
Regarding claim 19, Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 19 is dependent. Imai does not teach the first insulating element and the second insulating element including two resonance circuits.
Choe et al. teaches the insulating element being two resonance circuits (Fig. 1, Electromagnetic resonance coupler 100, first resonator 101, & second resonator 102; ¶56-58 & ¶100-101).
Imai and Choe et al. are analogous art as they are in the same field of endeavor of galvanic isolated circuits. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Imai to incorporate the teachings of Choe et al. to have the first and second insulating elements include two resonance circuits for the purpose of using magnetic resonance coupling to insulate the primary side circuit and secondary side circuit while avoiding issues associated with photocouplers such as being susceptible to heat, consuming large amounts of power, and deteriorating with time, as recognized by Choe et al.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of Akahane (Pub. No. US20180151796A1).
Imai teaches all the elements of claim 1, as stated above under the section Claim Rejections - 35 USC § 102, on which claim 20 is dependent. Imai does not teach the first insulating element and the second insulating element including an oscillator and an oscillation power generating device.
Akahane teaches the insulating element including an oscillator and an oscillating power generating device (Fig. 1, Transmitting circuit 11, receiving circuit 22, actuator 10, pressure sensor 20, sensor element 21, pressure propagation region 30, pressure 31, piezoelectric element 12, metal electrodes 13a & 13b; ¶69-75).
Imai and Akahane are analogous art as they are in the same field of endeavor of galvanic isolated circuits. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Imai to incorporate the teachings of Akahane to have the first and second insulating elements include an oscillator and oscillation power generating device for the purpose of insulating the primary side circuit and secondary side circuit, as recognized by Akahane.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Waki (US Patent No. 11,911,668) and Toshiba Electronic Devices & Storage Corporation's document titled "Photorelay Specifications".
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./ Examiner, Art Unit 2897