DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Species A(3), B(2), C(1), in the reply filed on 1/5/26 is acknowledged.
Status of the Application
Claim(s) 1-17 is/are pending.
Claim(s) 5, 9 is/are withdrawn.
Claim(s) 1-4, 6-8, 10-17 is/are rejected.
Specification Objections
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE FOR CHARGED PARTICLE BEAM CONTROL.
Claim Rejections – 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
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The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
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Claim(s) 1-4, 6-8, 10-17 is/are rejected under 35 U.S.C. § 112(b) or 35 U.S.C. § 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites “a plurality of second through holes provided on the first through holes” but it is unclear how the second through holes are provided on the first through holes. It is suggested that this geometric configuration is clarified.
Claim 1 recites “the second electrode and the fourth electrode are additional electrode patterns other than the first pair of electrodes and the second pair of electrodes for deflecting the charged particle beams” but it is unclear whether “for deflecting the charged particle beams” refers to the first and second pairs or the second and fourth electrodes.
Claims 2-4, 6-8, 10-17 are rejected due to their dependency from claim 1.
Claim Rejections – 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
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Claim(s) 1-4, 10-17 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Platzgummer (US 20150021493 A1) in view Platzgummer et al. (US 20150311031 A1) [hereinafter Platzgummer II].
Regarding claim 1, Platzgummer teaches a semiconductor device, comprising:
a first chip (see e.g. fig 11d: 512) having a first substrate surface (see top surface), a second substrate surface (see bottom surface) provided on a side opposite to the first substrate surface, and a plurality of first through holes (see 523), a plurality of charged particle beams passing through the first through holes (see e.g. [0080]);
a second chip (see e.g. 522) provided on the first chip (see fig 11d, alternately note obviousness of adjusting shape of chips) and having a third substrate surface (see top surface) facing the second substrate surface (see fig 11d), a fourth substrate surface (see bottom surface), and a plurality of second through holes provided on the first through holes (see 523), the charged particle beams passing through the second through holes;
a plurality of first electrodes (see e.g. 511) provided on the first substrate surface so as to be adjacent to the first through holes (see fig 11d);
a plurality of second electrodes (see e.g. 510) provided on the first substrate surface;
a plurality of third electrodes (see e.g. 521)
a plurality of fourth electrodes (see e.g. 520)
wherein the first electrodes are a first pair of electrodes for deflecting the charged particle beams (see fig 11d),
the third electrodes are a second pair of electrodes for deflecting the charged particle beams (see fig 11d),
the second electrode and the fourth electrode are additional electrode patterns other than the first pair of electrodes and the second pair of electrodes for deflecting the charged particle beams (see figs 11d, 11b-c), and
an electrode pattern formed by the first electrode and the second electrode on the first substrate surface and an electrode pattern formed by the third electrode and the fourth electrode on the fourth substrate surface are not symmetrical with respect to opposite substrate surfaces of the two chips (defining as different non-symmetrically configured electrodes in the array, see figs 11b-c).
Platzgummer may fail to explicitly disclose the third and fourth electrodes being provided on the fourth substrate surface.
However, the orientation of the deflection and control electrodes was well known in the art to be placed on either the upper or lower side of the aperture plate. For example, Platzgummer II teaches deflection aperture plates may be formed so that the electrodes are printed in either the upper or lower sides of the aperture plate, as known equivalents to each other (see Platzgummer II, figs 2a-2b, [0017]). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to form the electrode on either the third or fourth substrate surface in the system of the combined prior art, as a routine skill in the art, for example to enable easier mounting to some existing structure, to provide easier assembly by allowing visual inspection of electrodes contacts by not obfuscating the electrode side of one plate with the other. It is noted it has been held that a mere rearrangement of element without modification of the operation of the device would involve only routine skill in the art. See MPEP 2144.04; In re Japiske, 86 USPQ 70 (CCPA 1950). It is noted simple substitution of one known element for another to obtain predictable results supported a prima facie obviousness. See MPEP 2143.
Regarding claim 10, the combined teaching of Platzgummer and Platzgummer II teaches each of the first electrodes includes a pair of deflection electrode (see Platzgummer, e.g. fig 11d: 511) and ground electrode (see 510), a voltage being applied to the pair of deflection electrode and ground electrode (see e.g. [0081,84]), the second electrodes are arranged so as to surround at least some of the deflection electrodes of the first electrodes and the first through holes (see fig 11d; alternately see figs 11b-c), each of the third electrodes includes a pair of deflection electrode (see 521) and ground electrode (520), a voltage being applied to the pair of deflection electrode and ground electrode (see same), and the fourth electrodes are arranged so as to surround at least some of the deflection electrodes of the third electrodes and the second through holes (see same, figs 11d; 11b-c).
Regarding claim 11, the combined teaching of Platzgummer and Platzgummer II teaches each of the first electrodes includes a pair of deflection electrode (see Platzgummer, e.g. fig 11d: 511) and ground electrode (see 510), a voltage being applied to the pair of deflection electrode and ground electrode (see [0081,84]), each of the third electrodes includes a pair of deflection electrode (see 521) and ground electrode (see 520), a voltage being applied to the pair of deflection electrode and ground electrode (see same), and a pattern formed by the ground electrodes of the first electrodes and the second electrodes or a pattern formed by the ground electrodes of the third electrodes and the fourth electrodes surrounds the deflection electrodes of the first electrodes (see fig 11d; alternately see figs 11b-c), the deflection electrodes of the third electrodes, the first through holes, and the second through holes when viewed from above the second chip (see fig 11d; alternately see figs 11b-c).
Regarding claim 12, the combined teaching of Platzgummer and Platzgummer II teaches each of the first electrodes includes a pair of deflection electrode (see Platzgummer, e.g. fig 11d: 511) and ground electrode (see 510), a voltage being applied to the pair of deflection electrode and ground electrode (see [0081,84]), each of the third electrodes includes a pair of deflection electrode (see 521) and ground electrode (see 520), a voltage being applied to the pair of deflection electrode and ground electrode (see same), the second electrodes (redefining as pads, e.g. [0093]) are connected to the ground electrodes of the first electrodes (see 510, required for operation of system to connect to external voltage source), and the fourth electrodes (redefining as other pads) are connected to the ground electrodes of the third electrodes (see 521, required for operation of system to connect to external voltage source).
Regarding claim 13, the combined teaching of Platzgummer and Platzgummer II teaches each of the first electrodes includes a pair of deflection electrode (see Platzgummer, e.g. fig 11d: 511) and ground electrode (see 510), a voltage being applied to the pair of deflection electrode and ground electrode (see [0081,84]), each of the third electrodes includes a pair of deflection electrode (see 521) and ground electrode (see 520), a voltage being applied to the pair of deflection electrode and ground electrode (see same), the first through holes and the second through holes are positioned vertically corresponding to each other (see fig 11d). The combined teaching may fail to explicitly disclose a pattern formed by the ground electrodes of the third electrodes and the fourth electrodes provided on the fourth substrate has a shape obtained by rotating a pattern formed by the ground electrodes of the first electrodes and the second electrodes provided on the first substrate by 180 degrees within a plane parallel to the fourth substrate surface when viewed from an upper surface of the second chip. However, in a different embodiment, Platzgummer teaches that multiple chips may be rotated relative to each other in order to further reduce cross talk (see Platzgummer, [0087]) or as a routine skill in the art to arrange chips (see [0092]). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to adjust the relative orientation of the electrode patterns of the third and fourth electrodes, including a configuration at least in part substantially a rotation of the first and second electrodes, as a routine skill in the art, for example to try to further reduce cross talk, in the manner taught by Platzgummer. Additionally it is noted it has been held that a mere rearrangement of element without modification of the operation of the device would involve only routine skill in the art. See MPEP 2144.04; In re Japiske, 86 USPQ 70 (CCPA 1950).
Claim 14 is rejected for similar reasons as claim 13 above.
Claim 15 is rejected for similar reasons as claim 13 above.
Regarding claim 16, the combined teaching of Platzgummer and Platzgummer II teaches the second substrate surface and the third substrate surface are in contact with each other (see surfaces bonded together, Platzgummer, [0073]; alternately note some kind of support required for operation of system, requiring those respective surfaces to be in contact with each other).
Regarding claim 17, the combined teaching of Platzgummer and Platzgummer II teaches wherein trajectories of the charged particle beams are controlled (see e.g. Platzgummer, abstract).
Claim(s) 2-4, 6-8 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Platzgummer and Platzgummer II, as applied to claim 1 above, and further in view of Matsumoto (US 20160141142 A1).
Regarding claim 2, the combined teaching of Platzgummer and Platzgummer II may fail to explicitly disclose the claimed limitation. However, the use of pad and bump connections was well known in the art at the time the application was effectively filed (see e.g. Platzgummer, [0093]). For example, Matsumoto teaches a support interface system for supporting an aperture array system utilizing a plurality of pads (see Matsumoto, fig 4) which enables the ability to provide external signal conversion from differential to single ended signals, and reduce heat generation in the aperture array (see e.g. [0037]). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to combine the teachings of Matsumoto in the system of the prior art because a skilled artisan would have been motivated to look for ways to improve operation of the system, including enabling use of conversion circuitry to reduce heat generation in the aperture array, in the manner taught by Matsumoto. Therefore, the combined teaching of Platzgummer, Platzgummer II, and Matsumoto teaches wherein the second electrodes provided on the first substrate surface are a plurality of first pads (redefining as e.g. Matsumoto, fig 5: 29) electrically connected to the first electrodes (see e.g. [0035]), the fourth electrodes provided on the fourth substrate surface are a plurality of second pads (see fig 5: 29 for other plate) electrically connected to the third electrodes (see same), the first and second pads are arranged so as not to overlap each other when viewed from an upper surface of the second chip (note different pads, see e.g. [0035]), the first chip and the second chip are held by a support (required for intended operation of system, e.g. fig 3: 212), and the first and second pads are connected to pads (e.g. 506) provided on the support. It is unclear if all the first and second pads are arranged so as not to overlap each other when viewed from an upper surface of the second chip. However, it would have been obvious to adjust the positions of the pads as a routine design choice. It is noted it has been held that a mere rearrangement of element without modification of the operation of the device would involve only routine skill in the art. See MPEP 2144.04; In re Japiske, 86 USPQ 70 (CCPA 1950).
Regarding claim 3, the combined teaching of Platzgummer, Platzgummer II, and Matsumoto teaches the first and second pads (see Matsumoto, e.g. fig 5: 29) are electrically connected to the pads (see on e.g. fig 3: 506) provided on the support by using a plurality of wires (see wires inside circuit 219; alternately note obviousness of using at least some wires to connect circuitry components).
Regarding claim 4, the combined teaching of Platzgummer, Platzgummer II, and Matsumoto teaches the support has pads (see Matsumoto, e.g. fig 3: 506; see also 217b) provided on a first surface facing the first substrate surface, and is electrically connected to the first pads (see fig 3) through a plurality of bumps (see e.g. 218).
Regarding claim 6, the combined teaching of Platzgummer, Platzgummer II, and Matsumoto teaches the first chip has a rectangular shape (see Platzgummer, e.g. fig 15), the second chip has a rectangular shape (see same), the first pads are provided side by side at an end portion along a first direction parallel to the first substrate surface (see Platzgummer, [0093]; Matsumoto, fig 3-4), and the second pads are provided side by side at an end portion along a second direction parallel to the fourth substrate surface and crossing the first direction (see same; note it was well known in the art at the time the application was effectively filed to provide contacts on all four sides of the chip, and it additionally would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to select the use of different sides to provide the intended operation of connecting the chips to upstream circuitry; note flexibility of providing plates in any configuration using bumps, see Matsumoto, [0039-40]). Additionally it is noted it has been held that a mere rearrangement of element without modification of the operation of the device would involve only routine skill in the art. See MPEP 2144.04; In re Japiske, 86 USPQ 70 (CCPA 1950).
Claim 7 is rejected for similar reasons as claim 6 above.
Claim 8 is rejected for similar reasons as claim 6 above.
Conclusion
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/JAMES CHOI/Examiner, Art Unit 2881