DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, claims 1, 4-7, 9-15, and 17-20, in the reply filed on 12/29/2025 is acknowledged.
IDS
The IDS document(s) filed on 08/29/2023 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jia et al. (US 2020/0161415 A1), hereafter “Jia”.
As to claim 1, Jia teaches a semiconductor device comprising:
a semiconductor layer (104, Fig. 1, ⁋ [0015]);
a first conductive portion (112, ⁋ [0019]) provided in the semiconductor layer;
an insulating film (110, ⁋ [0018]) provided in the semiconductor layer and disposed between the semiconductor layer and the first conductive portion; and
a second conductive portion (114, ⁋ [0019]) provided in the semiconductor layer, disposed such that the first conductive portion is located between the second conductive portion and the insulating film, and electrically connected to the first conductive portion,
wherein the second conductive portion has residual stress (⁋ [0030], “a tensile stress layer”) with force components in directions opposite to directions of force components of residual stress of the first conductive portion (⁋ [0030], “a compressive stress layer”).
As to claim 9, Jia teaches the semiconductor device according to claim 1, wherein an electrical resistivity of the second conductive portion is lower than an electrical resistivity of the first conductive portion (⁋ [0020], “The second polysilicon layer 114 has a higher doping level as compared to the first polysilicon layer”).
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Okazaki.
As to claim 4, Jia teaches the semiconductor device according to claim 1, but fails to teach wherein the thickness of the second conductive portion is 0.2 to 5.0 times the thickness of the first conductive portion.
It would have been obvious to one of ordinary skill in the art to obtain the dimensions because if the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device: In re Gardner v. TEC Systems, Inc., 220 USPQ 777.
Claims 5-7, 12-15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Jia, and further in view of Okazaki et al. (US 2004/0038492 A1), hereafter “Okazaki”.
As to claim 5, Jia teaches the semiconductor device according to claim 1, but fails to explicitly teach wherein the semiconductor layer includes raised portions projecting in a first direction, the insulating film surrounds the side surfaces of the raised portions, the first conductive portion surrounds the side surfaces of the insulating film, and the second conductive portion surrounds the side surfaces of the first conductive portion.
Okazaki teaches a similar capacitor formed in a trench 4a (⁋ [0121], Fig. 3) formed in a semiconductor layer 8 with raised portions, i.e. portions of 8 located directly horizontal to 4a and contacting 15a. These raised portions project in a first direction vertically. Figs. 5 and 7 show the capacitor formation trenches 4a and the raised portions (located directly under the silicon nitride film 3 in Fig. 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the trench formation structure as taught by Okazaki to the device of Jia to improve the capacitor capacitance per unit area (⁋ [0133]).
Additionally, the combination of Okazaki’s trench formation of Fig. 7 and Jia’s device would teach the remaining limitations of the insulating film surrounds the side surfaces of the raised portions, the first conductive portion surrounds the side surfaces of the insulating film, and the second conductive portion surrounds the side surfaces of the first conductive portion.
As to claim 6, Jia in view of Okazaki teach the semiconductor device according to claim 5, Okazaki further teaches wherein in a plane perpendicular to the first direction, the raised portions each have a triangular shape, a quadrilateral shape, a hexagonal shape, or an octagonal shape (Fig. 7 shows the raised portion as a square however, it is mentioned stated in ⁋ [0133] “the pattern of the capacitor formation trenches 4a is not limited to the shape of holes, stripes, or a matrix, but a pattern in any other shape may also be adopted”).
As to claim 7, Jia teaches the semiconductor device according to claim 1, but fails to explicitly teach wherein the semiconductor layer includes a plurality of raised portions projecting in a first direction, and the raised portions are arranged side-by-side in a second direction perpendicular to the first direction and in a third direction perpendicular to the first direction and intersecting the second direction.
Okazaki teaches a similar capacitor formed in a trench 4a (⁋ [0121], Fig. 3) formed in a semiconductor layer 8 with raised portions, i.e. portions of 8 located directly horizontal to 4a and contacting 15a. These raised portions project vertically. Further it can be seen in Fig. 5 and 7, that these raised portions are arranged side-by-side in a second direction perpendicular to the first direction and in a third direction perpendicular to the first direction and intersecting the second direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the trench formation structure as taught by Okazaki to the device of Jia to improve the capacitor capacitance per unit area (⁋ [0133]).
As to claim 12, Jia teaches a semiconductor device comprising:
a semiconductor layer (104, Fig. 1, ⁋ [0015]);
an insulating film (110, ⁋ [0018]) disposed on upper and sidewall potions of the raised portions (Fig. 1);
a first conductive portion (112, ⁋ [0019]) disposed on the insulating film; and
a second conductive portion (114, ⁋ [0019]) disposed on the first conductive portion, wherein
the insulating film (110) is between the semiconductor layer (104) and the first conductive portion (112) and the first conductive portion is between the insulating film and the second conductive portion (Fig. 1), and
the first conductive portion has residual stress (⁋ [0030], “a compressive stress layer”) with first force components and the second conductive portion has residual stress (⁋ [0030], “a tensile stress layer”) with second force components, and directions of the first force components are opposite to directions of the second force components (compressive stress is opposite of tensile stress).
Jia fails to teach a semiconductor layer including a plurality of raised portions arranged in a lattice pattern.
Okazaki teaches a similar capacitor formed in a trench 4a (⁋ [0121], Fig. 3) formed in a semiconductor layer 8 with raised portions, i.e. portions of 8 located directly horizontal to 4a and contacting 15a, and arranged in a lattice pattern (⁋ [0132]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the trench formation structure and lattice pattern as taught by Okazaki to the device of Jia to improve the capacitor capacitance per unit area (⁋ [0133]).
As to claim 13, Jia in view of Okazaki teach the semiconductor device according to claim 12, wherein the first force components cause warping of the semiconductor device in a first direction (compressive stress pulls or operates in an inward direction) and the second force components cause warping of the semiconductor device in a second direction that is opposite to the first direction (tensile stress expands or operates in an outward direction).
As to claim 14, Jia in view of Okazaki teach the semiconductor device according to claim 12, but fails to teach wherein the thickness of the second conductive portion is 0.2 to 5.0 times the thickness of the first conductive portion.
On the other hand, it would have been obvious to one of ordinary skill in the art to obtain the dimensions because if the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device: In re Gardner v. TEC Systems, Inc., 220 USPQ 777.
As to claim 15, Jia in view of Okazaki teach the semiconductor device according to claim 12, Okazaki further teaches wherein the raised portions each have a triangular shape, a quadrilateral shape, a hexagonal shape, or an octagonal shape (Fig. 7 shows the raised portion as a square however, it is mentioned stated in ⁋ [0133] “the pattern of the capacitor formation trenches 4a is not limited to the shape of holes, stripes, or a matrix, but a pattern in any other shape may also be adopted”).
As to claim 17, Jia in view of Okazaki the semiconductor device according to claim 12, Jia further teaches wherein an electrical resistivity of the second conductive portion is lower than an electrical resistivity of the first conductive portion (⁋ [0020], “The second polysilicon layer 114 has a higher doping level as compared to the first polysilicon layer”).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jia, further in view of Sharangpani et al. (US 2016/0149002 A1), hereafter “Sharangpani”.
As to claim 10, Jia teaches the semiconductor device according to claim 1, wherein the first conductive portion comprises polysilicon (⁋ [0019], “a first polysilicon layer 112”).
Jia fails to disclose the second conductive portion comprises a metallic conductive portion.
Sharangpani teaches 2 conductive layers, a compressive stress layer 476 and a tensile stress layer 461 wherein the tensile stress layer comprises a metallic conductive portion (Ruthenium). Examiner notes the second conductive layer of Jia is also a tensile stress layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply Sharangpani’s teaching of the tensile stress layer containing Ruthenium into the device of Jia since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jia, in view of Sharangpani, and further in view of Lin et al. (US 2022/0352379 A1), hereafter “Lin”.
As to claim 11, Jia in view of Sharangpani teaches the semiconductor device according to claim 10, but fails to teach wherein the second conductive portion has a stacked structure comprising a film comprising titanium, a film comprising titanium nitride, and a film comprising tungsten.
However, Sharangpani does teach Ruthenium as the material for the second conductive portion which imparts a tensile stress.
Lin teaches an electrode layer (220, Fig. 5A, ⁋ [0071]) which may include any suitable electrically conductive material such as Titanium, Titanium Nitride, and Tungsten, and combinations of the same which impart a tensile stress (⁋ [0071]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply Lin’s teaching of the tensile stress layer containing a combination of Titanium, Titanium Nitride, and Tungsten into the device of Jia and Sharangpani because Lin teaches Ruthenium can be substituted for Titanium, Titanium Nitride, and Tungsten ( [0071]).
Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jia, in view of Okazaki, and further in view of Sharangpani.
As to claim 18, Jia in view of Okazaki the semiconductor device according to claim 12, Jia further teaches wherein the first conductive portion comprises polysilicon (⁋ [0019], “a first polysilicon layer 112”).
Jia fails to disclose the second conductive portion comprises a metallic conductive portion.
Sharangpani teaches 2 conductive layers, a compressive stress layer 476 and a tensile stress layer 461 wherein the tensile stress layer comprises a metallic conductive portion (Ruthenium). Examiner notes the second conductive layer of Jia is also a tensile stress layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply Sharangpani’s teaching of the tensile stress layer containing Ruthenium into the device of Jia and Okazaki since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Jia, in view of Okazaki, Sharangpani, and further in view of Lin.
As to claim 19, Jia in view of Okazaki and Sharangpani teach the semiconductor device according to claim 18, but fails to teach wherein the second conductive portion has a stacked structure comprising a film comprising titanium, a film comprising titanium nitride, and a film comprising tungsten.
However, Sharangpani does teach Ruthenium as the material for the second conductive portion which imparts a tensile stress.
Lin teaches an electrode layer (220, Fig. 5A, ⁋ [0071]) which may include any suitable electrically conductive material such as Titanium, Titanium Nitride, and Tungsten, and combinations of the same which impart a tensile stress (⁋ [0071]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply Lin’s teaching of the tensile stress layer containing a combination of Titanium, Titanium Nitride, and Tungsten into the device of Jia, Okazaki and Sharangpani because Lin teaches Ruthenium can be substituted for Titanium, Titanium Nitride, and Tungsten (⁋ [0071]).
Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jia, in view of Okazaki, Sharangpani, and further in view of Yamamoto et al. (2017/0250029), hereafter “Yamamoto”.
As to claim 20, Jia in view of Okazaki and Sharangpani teach the semiconductor device according to claim 18, wherein an upper surface of the second conductive portion is planar.
However, Jia fails to teach a planar conductive layer is disposed on the upper surface of the second conductive portion.
Yamamoto teaches a similar device wherein a n-type polysilicon film 22 is laminated with a planar metal film 23 (⁋ [0144], Fig. 8C).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the planar metal film teaching of Yamamoto into the device of Jia, Okazaki, and Sharangpani to serve as a pad region portion for the capacitor component (⁋ [0145]).
Conclusion
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893