DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed May 14, 2026. Claims 1-2, 5, 7-9, and 16 have been amended. No claims have been added. Claims 4, 6, and 11-15 have been canceled. Currently, claims 1-3, 5, 7-10, and 16-20 are pending.
Response to Arguments
Applicant's arguments filed May 14, 2026 have been fully considered but they are not persuasive.
Applicant asserts that Yamamoto fails to disclose the limitation “a first recess having a first depth… a plurality of second recesses, each having a second depth substantially equal to the first depth”. The Examiner respectfully disagrees with this assertion as Fig. 2 of Yamamoto shows recesses between the microlenses which correspond to the second recesses and a recessed portion between the photodiodes which corresponds to the first recesses. The figure shows that the depth of the two recesses is “substantially equal”, as required by claim 1.
Applicant’s arguments with respect to the newly added limitation of claim 1 that the plurality of second recesses are “at locations respectively corresponding to and directly above the first and second photodiodes in the thickness direction of the semiconductor substrate” have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Newly amended claim 1 requires that the second recesses (RE2) have “a second depth substantially equal to the first depth” of the first recess (RE1) as shown in at least Figs. 1B and 1C. Claim 5, which depends upon claim 1, further requires that the semiconductor substrate (2) is exposed on a bottom surface of the first recess (RE1) as shown in at least Figs. 7B and 7C. However, there is no figure that shows both the recesses having substantially the same depth and the semiconductor substrate being exposed on a bottom surface of the first recess. Therefore, all the limitations of claim 5 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Newly amended claim 16 requires that the first (RE1) and second recesses (RE2) be “substantially equal in depth” as shown in at least Figs. 1B and 1C. Claim 18, which depends upon claim 16, further requires that the semiconductor substrate (2) is exposed on a bottom surface of the first recess (RE1) as shown in at least Figs. 7B and 7C. However, there is no figure that shows both the recesses having substantially the same depth and the semiconductor substrate being exposed on a bottom surface of the first recess. Therefore, all the limitations of claim 18 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 5, the claim recites the limitation “the semiconductor substrate is exposed on a bottom surface of the first recess” in line 2. Claim 1 provides antecedent basis for the first recess and defines it as substantially the same depth as the second recesses. It is unclear how the semiconductor substrate can be exposed on a bottom surface of the first recess while simultaneously being substantially the same depth as the second recesses which are positioned “directly above the first and second photodiodes in the thickness direction”.
Regarding claim 18, the claim recites the limitation “the semiconductor substrate is exposed on a bottom surface of the first recess” in line 2. Claim 1 provides antecedent basis for the first recess and defines it as substantially the same depth as the second recesses. It is unclear how the semiconductor substrate can be exposed on a bottom surface of the first recess while simultaneously being substantially the same depth as the second recesses which are positioned “directly above the first and second photodiodes in the thickness direction”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7, 16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 20170236860 A1) herein after “Yamamoto” in view of Nakamura et al. (JP 2019080079 A) herein after “Nakamura”.
Regarding claim 1, Figs. 1 and 7 of Yamamoto discloses a solid-state imaging device (Fig. 1, CMOS image sensor 30, ¶ [0157]), comprising:
a semiconductor substrate (Fig. 2, silicon substrate 73, ¶ [0174]) that includes a first region (Fig. 2, chip 70-2, ¶ [0205]) in which a plurality of first photodiodes (see Annotation 1, Fig. 2 of Yamamoto, PD1) are arranged along a first direction, and a second region (Fig. 2, chip 70-1, ¶ [0205]) in which a plurality of second photodiodes (see Annotation 1, Fig. 2 of Yamamoto, PD2) are arranged along the first direction; and
an insulating film (Fig. 2, “The microlens layer 79 is an inorganic material layer and made of SiN, SiO, or SiOxNy”, ¶ [0177]) that is disposed on the semiconductor substrate (73) to cover the first region (70-2) and the second region (70-1),
wherein the insulating film (79) includes:
a first recess (see Annotation 1, Fig. 2 of Yamamoto, R1) having a first depth (see Annotation 1, Fig. 2 of Yamamoto, RD) at a location that is directly above an intermediate region (see Annotation 1, Fig. 2 of Yamamoto, IR) in a thickness direction of the semiconductor substrate (73), wherein the intermediate region (IR) is between a first edge photodiode (see Annotation 1, Fig. 2 of Yamamoto, E1) closest to the second region (70-1) among the plurality of first photodiodes (PD1) and a second edge photodiode (see Annotation 1, Fig. 2 of Yamamoto, E2) closest to the first region (70-2) among the plurality of second photodiodes (PD2) in the first direction; and
a plurality of second recesses (see Annotation 1, Fig. 2 of Yamamoto, R2), each having a second depth (RD) substantially equal to the first depth, at locations respectively corresponding to the first (PD1) and second photodiodes (PD2) in the thickness direction of the semiconductor substrate (73).
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Annotation 1, Fig. 2 of Yamamoto
Yamamoto fails to disclose the second recesses directly above the photodiodes in the thickness direction of the semiconductor substrate.
In the similar field or endeavor of photoelectric conversion elements, Fig. 1 of Nakamura discloses the second recesses (Fig. 1, recess 51A, ¶ [0019]) directly above the photodiodes (Fig. 1, photodiode 20, ¶ [0014]) in the thickness direction of the semiconductor substrate (Fig. 1, silicon substrate 10, ¶ [0016]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yamamoto with the second recesses as disclosed by Nakamura, to obtain the desired scattering properties (see Nakamura, ¶ [0021]).
Regarding claim 2, Yamamoto and Nakamura together disclose the solid-state imaging device according to claim 1 as applied above, and Fig. 2 of Yamamoto further discloses wherein the first recess (R1) provided in the insulating film (79) in the intermediate region (IR) changes an optical path of light incident on the insulating film on the first region and directed to the second region (Yamamoto discloses the recess structure as required by the claims, therefore Yamamoto anticipates the effect of changing the optical path).
Regarding claim 3, Yamamoto and Nakamura together disclose the solid-state imaging device according to claim 2 as applied above, and Figs. 2 and 7 of Yamamoto further discloses wherein the first recess (R1) corresponds to a dicing line (Fig. 2, scribe section 91-1, ¶ [0180]) for dicing performed when the solid-state imaging device is segmented into a plurality of chips (“dicing is performed along the scribe section 91-1 and the scribe section 91-2, and thus the diced chip 110 is manufactured”, ¶ [0268]).
Regarding claim 5, Yamamoto and Nakamura together discloses the solid-state imaging device according to claim 1 as applied above, and Fig. 2 of Yamamoto further discloses wherein the semiconductor substrate (73) is exposed on a bottom surface of the first recess (R1).
Regarding claim 7, Yamamoto and Nakamura together disclose the solid-state imaging device according to claim 1 as applied above, and Fig. 2 of Yamamoto further discloses wherein the first recess (R1) extends in a second direction substantially orthogonal to the first direction and the thickness direction of the semiconductor substrate (73).
Regarding claim 16, Figs. 1 and 2 of Yamamoto discloses a solid-state imaging device (30), comprising:
a semiconductor substrate (73) that includes a first region (70-1) in which a plurality of first photodiodes (PD1) are arranged along a first direction, and a second region (70-2) in which a plurality of second photodiodes (PD2) are arranged along the first direction; and
an insulating film (79) that is disposed on the semiconductor substrate (73) to cover the first region (70-1) and the second region (70-2),
wherein an upper surface of the insulating film (79) includes a first recess (R1) at a location that is between the first (70-1) and second regions (70-2) in the first direction and second recesses (R2) at locations respectively corresponding to first (PD1) and second photodiodes (PD2) in a thickness direction of the semiconductor substrate (73), the first recess (R1) extending in a second direction that crosses the first direction and orthogonal to the thickness direction of the semiconductor substrate (73) and having a depth that is substantially equal to a depth each of the second recesses (R2).
Yamamoto fails to disclose the second recesses directly above the photodiodes in the thickness direction of the semiconductor substrate.
In the similar field or endeavor of photoelectric conversion elements, Fig. 1 of Nakamura discloses the second recesses (51A) directly above the photodiodes (20) in the thickness direction of the semiconductor substrate (10).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yamamoto with the second recesses as disclosed by Nakamura, to obtain the desired scattering properties (see Nakamura, ¶ [0021]).
Regarding claim 18, Yamamoto and Nakamura together discloses the solid-state imaging device according to claim 16 as applied above, and Fig. 2 of Yamamoto further discloses wherein the semiconductor substrate (73) is exposed on a bottom surface of the first recess (R1).
Regarding claim 19, Yamamoto and Nakamura together discloses the solid-state imaging device according to claim 16 as applied above, and Fig. 2 of Yamamoto further discloses wherein the first recess (R1) is one of a plurality of recesses that extend in the second direction to both ends of the insulating film (79) in the second direction (Fig. 2 of Yamamoto shows at least two recesses that extend in the second direction).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 20170236860 A1) and Nakamura (JP 2019080079 A) in view of Yukawa et al. (US 20220262839 A1) herein after “Yukawa”.
Regarding claim 8, Yamamoto and Nakamura together disclose the solid-state imaging device according to claim 7 as applied above, but the combination fails to explicitly disclose wherein the first recess extends in the second direction to edges of the solid-state imaging device in the second direction.
In the similar field of solid-state imaging devices, Fig. 7 of Yukawa discloses wherein the first recess (Fig. 7, light shielding layer 134, ¶ [0124]) extends in the second direction to edges of the solid-state imaging device (Fig. 7, solid-state imaging device 100, ¶ [0067]) in the second direction.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the imaging device of Yamamoto with the optical path changing portion as disclosed by Yukawa, to suppress the image quality degradation (see Yukawa, ¶ [0126]).
Regarding claim 9, Yamamoto and Nakamura together discloses the solid-state imaging device according to claim 7 as applied above, but the combination fails to explicitly disclose wherein the first recess surrounds the plurality of first photodiodes.
In the similar field of solid-state imaging devices, Fig. 7 of Yukawa discloses wherein the first recess (134) surrounds the plurality of first photodiodes (Fig. 7, effective pixel region 141, ¶ [0113]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the imaging device of Yamamoto with the optical path changing portion as disclosed by Yukawa, to suppress the image quality degradation (see Yukawa, ¶ [0126]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 20170236860 A1) and Nakamura (JP 2019080079 A) in view of Endo et al. (US 20070252225 A1) herein after “Endo”.
Regarding claim 10, Yamamoto and Nakamura together disclose the solid-state imaging device according to claim 1 as applied above, and Yamamoto further discloses “the present technology can be applied even to other types of solid state imaging devices”, ¶ [1351], but the combination fails to explicitly disclose the solid-state imaging device is a linear image sensor, and
a circuit and/or a wiring for the linear image sensor is not disposed between the first edge photodiode and the second edge photodiode.
In the similar field of image sensor, Fig. 4 of Endo discloses the solid-state imaging device is a linear image sensor (“a linear image sensor of a multi-chip type in which a plurality of semiconductor chips”, ¶ [0004]), and
a circuit and/or a wiring for the linear image sensor is not disposed between the first edge photodiode and the second edge photodiode (“A reference symbol Lgap denotes a gap portion (gap) between the adjacent sensor chips 6, and [11e] denotes image pickup elements (boundary image pickup elements) located at the both ends of the semiconductor chips 6”, ¶ [0063]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to substitute the imaging device of Yamamoto with the linear image sensor as disclosed by Endo. The claimed linear image sensor was known in the prior art and one skilled in the art could have combined the Yamamoto with the linear elements of Endo with no change in their respective functions, and the combination would have yielded the predictable result of creating an accurate image sensor. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 20170236860 A1) and Nakamura (JP 2019080079 A) in view of Hagiwara (US 20060170800 A1) and Yukawa (US 20220262839 A1).
Regarding claim 17, Yamamoto and Nakamura together discloses the solid-state imaging device according to claim 16 as applied above, but the combination fails to explicitly disclose wherein the first recess extends in the second direction to both ends of the insulating film in the second direction.
In the similar field of endeavor of solid state image pickup devices, Fig. 5A of Hagiwara discloses the first recess (Figs. 5A-5B, between base 27 and micro lens 85) of the optical path changing portion extends in the second direction in the insulating film (Figs. 5A-5B, base 27, ¶ [0018]) in the second direction.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the imaging device of Yamamoto with the recesses as disclosed by Hagiwara, to improve manufacture quality (see Hagiwara, ¶ [0054]).
Hagiwara fails to disclose the optical path changing portion extends to both ends of the insulating film.
In the similar field of solid-state imaging devices, Fig. 7 of Yukawa discloses wherein the optical path changing portion (134) extends to both ends of the insulating film (Fig. 7, glass substrate 133, ¶ [0114]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the imaging device of Yamamoto with the optical path changing portion as disclosed by Yukawa, to suppress the image quality degradation (see Yukawa, ¶ [0126]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 20170236860 A1) and Nakamura (JP 2019080079 A) in view of Hagiwara (US 20060170800 A1).
Regarding claim 20, Yamamoto and Nakamura together discloses the solid-state imaging device according to claim 16 as applied above, but the combination fails to explicitly disclose wherein the first recess is a part of a rectangular recess that surrounds the plurality of first photodiodes.
In the In the similar field of endeavor of solid state image pickup devices, Fig. 5A of Hagiwara discloses wherein the first recess (Figs. 5A-5B, between base 27 and micro lens 85) is a part of a rectangular recess that surrounds the plurality of first photodiodes (26) (shown in Fig. 5A).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the imaging device of Yamamoto with the recesses as disclosed by Hagiwara, to improve manufacture quality (see Hagiwara, ¶ [0054]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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