DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, Species A corresponding to claims 1-10 and 16-20 in the reply filed on December 30, 2025 is acknowledged.
Claims 11-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 30, 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 16, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto et al. (US 20170236860 A1) herein after “Yamamoto”.
Regarding claim 1, Figs. 1 and 7 of Yamamoto discloses a solid-state imaging device (Fig. 1, CMOS image sensor 30, ¶ [0157]), comprising:
a semiconductor substrate (Fig. 7, silicon substrate 73, ¶ [0174]) that includes a first region (Fig. 7, chip 120-1, ¶ [0205]) in which a plurality of first photodiodes (see Annotation 1, Fig. 7 of Yamamoto, PD1) are arranged along a first direction, and a second region (Fig. 7, chip 120-2, ¶ [0205]) in which a plurality of second photodiodes (see Annotation 1, Fig. 7 of Yamamoto, PD2) are arranged along the first direction; and
an insulating film (Fig. 7, “The microlens layer 79 is an inorganic material layer and made of SiN, SiO, or SiOxNy”, ¶ [0177]) that is disposed on the semiconductor substrate (73) to cover the first region (120-1) and the second region (120-2),
wherein the insulating film (79) includes an optical path changing portion (Fig. 7, groove 121-1, ¶ [0206]) that changes an optical path of light incident on the insulating film (79) on the first region (120-1) and directed to the second region (120-2) in at least an intermediate region (region between 120-2 and 120-1) between a first edge photodiode (see Annotation 1, Fig. 7 of Yamamoto, E1) closest to the second region (120-2) among the plurality of first photodiodes (PD1) and a second edge photodiode (see Annotation 1, Fig. 7 of Yamamoto, E2) closest to the first region (120-1) among the plurality of second photodiodes (PD2).
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Annotation 1, Fig. 7 of Yamamoto
Regarding claim 2, Figs. 1 and 7 of Yamamoto disclose the solid-state imaging device according to claim 1 as applied above, and Fig. 7 further discloses wherein the optical path changing portion (121-1) is a first recess (see Annotation 1, Fig. 7 of Yamamoto, R1) provided in the insulating film (79) in the intermediate region (region between 120-2 and 120-1).
Regarding claim 3, Fig. 7 of Yamamoto discloses the solid-state imaging device according to claim 2 as applied above, and Figs. 2 and 7 further discloses wherein the first recess (R1) corresponds to a dicing line (Fig. 2, scribe section 91-1, ¶ [0180]) for dicing performed when the solid-state imaging device is segmented into a plurality of chips (“dicing is performed along the scribe section 91-1 and the scribe section 91-2, and thus the diced chip 110 is manufactured”, ¶ [0268]).
Regarding claim 4, Fig. 7 of Yamamoto discloses the solid-state imaging device according to claim 2 as applied above, and Fig. 7 further discloses wherein
the insulating film (79) includes a plurality of second recesses (see Annotation 1, Fig. 7 of Yamamoto, R2) in locations corresponding to the plurality of first photodiodes (PD1) and the plurality of second photodiodes (PD2), and
a depth of the first recess (R1) is greater than or equal to a depth of the second recess (R2).
Regarding claim 5, Fig. 7 of Yamamoto discloses the solid-state imaging device according to claim 4 as applied above, and Fig. 7 further discloses wherein the semiconductor substrate (73) is exposed on a bottom surface of the first recess (R1).
Regarding claim 6, Figs. 1 and 7 of Yamamoto disclose the solid-state imaging device according to claim 1 as applied above, and Fig. 7 further discloses wherein the optical path changing portion (121-1) is buried in the insulating film (79), and is made of a material having a refractive index different from a refractive index of the insulating film (79) (Yamamoto discloses “The microlens layer 79 is an inorganic material layer and made of SiN, SiO, or SiOxNy”, ¶ [0177], and the optical path changing portion contains an air gap, ¶ [0208] which would have a refractive index different from the insulating material of 79).
Regarding claim 7, Figs. 1 and 7 of Yamamoto disclose the solid-state imaging device according to claim 1 as applied above, and Fig. 7 further discloses wherein the optical path changing portion (121-1) crosses the intermediate region (region between 120-2 and 120-1) in a second direction substantially orthogonal to the first direction.
Regarding claim 16, Figs. 1 and 7 of Yamamoto discloses a solid-state imaging device (30), comprising:
a semiconductor substrate (73) that includes a first region (120-1) in which a plurality of first photodiodes (PD1) are arranged along a first direction, and a second region (120-2) in which a plurality of second photodiodes (PD2) are arranged along the first direction; and
an insulating film (79) that is disposed on the semiconductor substrate (73) to cover the first region (120-1) and the second region (120-2),
wherein an upper surface of the insulating film (79) includes a first recess (R1) at a location that is between the first (120-1) and second regions (120-2) and second recesses (R2) at locations directly above the first and second photodiodes (PD2) in a thickness direction of the semiconductor substrate (73), the first recess (R1) extending in a second direction that crosses the first direction and orthogonal to the thickness direction of the semiconductor substrate (73) and having a depth that is greater than or equal to a depth of the second recesses (R2).
Regarding claim 18, Figs. 1 and 7 of Yamamoto discloses the solid-state imaging device according to claim 16 as applied above, and Fig. 7 further discloses wherein the semiconductor substrate (73) is exposed on a bottom surface of the first recess (R1).
Regarding claim 19, Figs. 1 and 7 of Yamamoto discloses the solid-state imaging device according to claim 16 as applied above, and Fig. 7 further discloses wherein the first recess (R1) is one of a plurality of recesses that extend in the second direction to both ends of the insulating film (79) in the second direction (Fig. 7 of Yamamoto shows at least two recesses that extend in the second direction).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 20170236860 A1) in view of Yukawa et al. (US 20220262839 A1) herein after “Yukawa”.
Regarding claim 8, Fig. 7 of Yamamoto discloses the solid-state imaging device according to claim 7 as applied above, but Yamamoto fails to explicitly disclose wherein the optical path changing portion extends along the second direction orthogonal to the first direction to edges of the solid-state imaging device in the second direction.
In the similar field of solid-state imaging devices, Fig. 7 of Yukawa discloses wherein the optical path changing portion (Fig. 7, light shielding layer 134, ¶ [0124]) extends along the second direction orthogonal to the first direction to edges of the solid-state imaging device (Fig. 7, solid-state imaging device 100, ¶ [0067]) in the second direction.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the imaging device of Yamamoto with the optical path changing portion as disclosed by Yukawa, to suppress the image quality degradation (see Yukawa, ¶ [0126]).
Regarding claim 9, Fig. 7 of Yamamoto discloses the solid-state imaging device according to claim 7 as applied above, but Yamamoto fails to explicitly disclose wherein the optical path changing portion surrounds the plurality of first photodiodes.
In the similar field of solid-state imaging devices, Fig. 7 of Yukawa discloses wherein the optical path changing portion (134) surrounds the plurality of first photodiodes (Fig. 7, effective pixel region 141, ¶ [0113]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the imaging device of Yamamoto with the optical path changing portion as disclosed by Yukawa, to suppress the image quality degradation (see Yukawa, ¶ [0126]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 20170236860 A1) in view of Endo et al. (US 20070252225 A1) herein after “Endo”.
Regarding claim 10, Figs. 1 and 7 of Yamamoto disclose the solid-state imaging device according to claim 1 as applied above, and Yamamoto further discloses “the present technology can be applied even to other types of solid state imaging devices”, ¶ [1351], but fails to explicitly disclose the solid-state imaging device is a linear image sensor, and
a circuit and/or a wiring for the linear image sensor is not disposed between the first edge photodiode and the second edge photodiode.
In the similar field of image sensor, Fig. 4 of Endo discloses the solid-state imaging device is a linear image sensor (“a linear image sensor of a multi-chip type in which a plurality of semiconductor chips”, ¶ [0004]), and
a circuit and/or a wiring for the linear image sensor is not disposed between the first edge photodiode and the second edge photodiode (“A reference symbol Lgap denotes a gap portion (gap) between the adjacent sensor chips 6, and [11e] denotes image pickup elements (boundary image pickup elements) located at the both ends of the semiconductor chips 6”, ¶ [0063]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to substitute the imaging device of Yamamoto with the linear image sensor as disclosed by Endo. The claimed linear image sensor was known in the prior art and one skilled in the art could have combined the Yamamoto with the linear elements of Endo with no change in their respective functions, and the combination would have yielded the predictable result of creating an accurate image sensor. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 20170236860 A1) in view of Hagiwara (US 20060170800 A1) and Yukawa (US 20220262839 A1).
Regarding claim 17, Figs. 1 and 7 of Yamamoto discloses the solid-state imaging device according to claim 16 as applied above, but Yamamoto fails to explicitly disclose wherein the first recess extends in the second direction to both ends of the insulating film in the second direction.
In the similar field of endeavor of solid state image pickup devices, Fig. 5A of Hagiwara discloses the first recess (Figs. 5A-5B, between base 27 and micro lens 85) of the optical path changing portion extends in the second direction in the insulating film (Figs. 5A-5B, base 27, ¶ [0018]) in the second direction.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the imaging device of Yamamoto with the recesses as disclosed by Hagiwara, to improve manufacture quality (see Hagiwara, ¶ [0054]).
Hagiwara fails to disclose the optical path changing portion extends to both ends of the insulating film.
In the similar field of solid-state imaging devices, Fig. 7 of Yukawa discloses wherein the optical path changing portion (134) extends to both ends of the insulating film (Fig. 7, glass substrate 133, ¶ [0114]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the imaging device of Yamamoto with the optical path changing portion as disclosed by Yukawa, to suppress the image quality degradation (see Yukawa, ¶ [0126]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 20170236860 A1) in view of Hagiwara (US 20060170800 A1).
Regarding claim 20, Figs. 1 and 7 of Yamamoto discloses the solid-state imaging device according to claim 16 as applied above, but Yamamoto fails to explicitly disclose wherein the first recess is a part of a rectangular recess that surrounds the plurality of first photodiodes.
In the In the similar field of endeavor of solid state image pickup devices, Fig. 5A of Hagiwara discloses wherein the first recess (Figs. 5A-5B, between base 27 and micro lens 85) is a part of a rectangular recess that surrounds the plurality of first photodiodes (26) (shown in Fig. 5A).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the imaging device of Yamamoto with the recesses as disclosed by Hagiwara, to improve manufacture quality (see Hagiwara, ¶ [0054]).
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893