Prosecution Insights
Last updated: April 19, 2026
Application No. 18/458,122

INTERCONNECTION MEMBER AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §103§112
Filed
Aug 29, 2023
Examiner
MCDONALD, JASON ANDREW
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toshiba Electronic Devices & Storage Corporation
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
1 granted / 1 resolved
+32.0% vs TC avg
Strong +100% interview lift
Without
With
+100.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
44 currently pending
Career history
45
Total Applications
across all art units

Statute-Specific Performance

§103
55.8%
+15.8% vs TC avg
§102
25.5%
-14.5% vs TC avg
§112
16.8%
-23.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I, Species A in the reply filed on 23 December 2025 is acknowledged. Information Disclosure Statement The Information Disclosure Statements (IDS) submitted on 29 August 2023 and 12 November 2024 have been considered by the examiner and made of record in the application file. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 1-8 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “continuous” in claim 1 is used by the claim to mean “in contact”, “connecting” or “contiguous”, while the accepted meaning is “uninterrupted.” The term is indefinite because the specification does not clearly redefine the term. There are clearly boundaries of the fifth face as described, and it is interrupted at those boundaries. For the purpose of examination, the term --continuous-- will be replaced with --contiguous--. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220130725 A1, hereinafter “Lee”), in view of Matsumoto et al (US 20160064178 A1, hereinafter “Matsumoto”). Regarding Claim 1 – Lee discloses an interconnection member comprising: a substrate (100 [0023] and Fig. 4) including a first face (First in annotated Fig. 3), a second face (Second in annotated Fig. 4) positioned on an opposite side with respect to the first face in a first direction, and a first through hole extending in the first direction (116 [0028] and Fig. 4); and an interconnection portion (Interconnection in annotated Fig. 4) provided on the first face of the substrate, including an insulating layer (Combination of 110 and 111 [0026] and Fig. ), an interconnection layer provided in the insulating layer (considered as “other metal interconnects and metal bumps” [0026]), a second through hole (216 in annotated Fig. 4) extending in the first direction and contiguous with the first through hole, and a conductive film (112 [0026] and Fig. 4) provided on a side surface of the second through hole, a width of the first through hole (W1 in annotated Fig. 4) being greater than a width of the second through hole (W2 in annotated Fig. 4) in a direction orthogonal to the first direction (W1>W2 in annotated Fig. 4), the first through hole also extending to a part of the interconnection portion in the first direction (116 extends to 110 as in Fig. 4), and a side surface of the first through hole including a first side surface portion positioned on the substrate (1st Side in annotated Fig. 4), and the interconnection portion including a third face facing the first face of the substrate (Third in annotated Fig. 4), a fourth face (Fourth in annotated Fig. 4) positioned on an opposite side with respect to the third face in the first direction, and a fifth face (Fifth in annotated Fig. 4), including an end surface of the conductive film in the first direction. Lee fails to disclose a second side surface portion positioned on the part of the interconnection portion, the fifth face contiguous with the second side surface portion of the first through hole and a side surface of the conductive film. However, Matsumoto discloses a second side surface portion (Second in annotated Matsumoto Fig. 5B) positioned on the part of the interconnection portion (Combination of 10 and 12, Matsumoto [0046] and annotated Fig. 5B), the fifth face contiguous with the second side surface portion of the first through hole and a side surface of the conductive film (Fifth contiguous with Second and Side in annotated Matsumoto Fig. 5B). Matsumoto also discloses a structure with through holes having a conductor covering at least a portion of an insulated layer. Matsumoto teaches an overhang of the conductive film not touching the whole side of the second side surface portion of the first through hole for the benefit of reduced probability of sidewall charging (Matsumoto [0049]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Lee and Matsumoto to form an overhang of the conductive film not touching the whole side of the second side surface portion of the first through hole for the benefit of reduced probability of sidewall charging. PNG media_image1.png 542 677 media_image1.png Greyscale PNG media_image2.png 355 521 media_image2.png Greyscale Regarding Claim 2 – Lee modified by Matsumoto discloses all the limitations of claim 1. The combination of Lee and Matsumoto further discloses the fifth face of the interconnection portion includes the end surface of the conductive film (as shown in Lee Fig. 4), and a surface of the insulating layer positioned on a side closer to the second side surface portion of the first through hole than the end surface of the conductive film in the direction orthogonal to the first direction. Regarding Claim 3 – Lee modified by Matsumoto discloses all the limitations of claim 1. The combination of Lee and Matsumoto further discloses a part of the fifth face of the interconnection portion includes only the end surface of the conductive film, and does not include the surface of the insulating layer on a second side surface portion side (Fifth in Matsumoto Fig. 5B only includes the end surface of conductive film 24). Regarding Claim 4 – Lee modified by Matsumoto discloses all the limitations of claim 1. The combination of Lee and Matsumoto further discloses the conductive film is a titanium film, a titanium nitride film, or a stacked film of a titanium film and a titanium nitride film (Lee [0026]). Regarding Claim 5 – Lee modified by Matsumoto discloses all the limitations of claim 1. The combination of Lee and Matsumoto further discloses the conductive film continuously covers an entire side surface of the second through hole (112, Lee [0026] and Fig. 4). Regarding Claim 6 – Lee modified by Matsumoto discloses all the limitations of claim 1. The combination of Lee and Matsumoto further discloses the insulating layer of the interconnection portion is not exposed on the side surface of the second through hole (Covered by 112, Lee [0026] and Fig. 4). Regarding Claim 8 – Lee modified by Matsumoto discloses all the limitations of claim 1. The combination of Lee and Matsumoto further discloses the conductive film is also provided on the fourth face of the interconnection portion (114, Lee [0026] and Fig. 4). Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220130725 A1, hereinafter “Lee”), in view of Matsumoto et al (US 20160064178 A1, hereinafter “Matsumoto”), and further in view of Iijima et al (US 20200243591 A1, hereinafter “Iijima). Regarding Claim 7 – Lee modified by Matsumoto discloses all the limitations of claim 1. The combination of Lee and Matsumoto fails to disclose the fifth face is annularly formed between the side surface of the conductive film and the second side surface portion of the first through hole. However, Iijima discloses the fifth face (Fifth in annotated Iijima Fig. 6D) is annularly formed between the side surface of the conductive film (Side in annotated Iijima Fig. 6D) and the second side surface portion of the first through hole (Second Side Surface in annotated Iijima Fig. 6D). Iijima is analogous to Lee in disclosing aligned through holes with larger width in the substrate, comprising a conductive film. Iijima teaches extending the first through hole a distance into the interconnection portion to form a second side surface portion with an annular fifth face for the benefit of the conductive film electrically connecting predetermined wring lines in stacked substrates (Iijima [0286]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Lee and Iijima to form a second side surface portion with an annular fifth face for the benefit of the conductive film electrically connecting predetermined wring lines in stacked substrates. PNG media_image3.png 647 563 media_image3.png Greyscale Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571)272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Aug 29, 2023
Application Filed
Mar 06, 2026
Non-Final Rejection — §103, §112 (current)

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+100.0%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 1 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month