DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-15) in the reply filed on 12/26/25 is acknowledged.
Claims 16-31 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/26/25.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 432-1, 432-2. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the gate of the first transistor and the WL gate of the WL transistor are formed from a common gate layer (claim 5) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 thru 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In last line of claim 1, the applicant states the limitation “including a corresponding second gate oxide layer having nitridation”; however, it is unclear what the applicant means by the term “nitridation” and what final structure is formed by having a “second gate oxide layer having nitridation.” For example, in “nitridation”, it is unclear whether this includes the layer becoming an oxynitride layer or being just exposed to ammonia, NH3 (and still be an oxide layer), for example, qualifies as “nitridation.” The specification does not give further clarification regarding “nitridation” and its metes and bounds. Appropriate clarification and/or correction are required.
In claim 5, the applicant states the limitation “the gate of the first transistor and the WL gate of the WL transistor are formed from a common gate layer”; however, it appears (see, for example, FIG. 2B) the gate of the first transistor and the WL gate are formed from a different gate layer. Appropriate clarification and/or correction are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
In view of the 112 rejection above, claim(s) 1 thru 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. US 2016/0042957 A1. Chang discloses (see, for example, FIG. 8) an integrated circuit comprising a substrate 100 including a first region 20/10, second region 30, flash memory cell gate stack 10, first transistor 20 including a gate 126b and first gate oxide layer 120, second transistor 30 including a second gate oxide 124. In paragraph [0017], Chang discloses the first region 20 being a high voltage device (i.e. operable at first voltage level) and the second region 30 being a low voltage device area (i.e. operable at a second voltage level). In paragraph [0027], Chang discloses second gate oxide 124 in the second transistor 30 is formed with decoupled plasma nitridation.
Regarding claim 2, see, for example, paragraph [0024] wherein Chang discloses the first oxide layer 120 being in the range of 160 to 180 A.
Regarding claim 3, see, for example, paragraph [0027] wherein Chang discloses the second oxide layer 124 being in the range of 20 to 40 A.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 thru 9, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. US 2016/0042957 A1 as applied to claims 1-3 above, and further in view of Chuang et al. US 2015/0137207 A1. Chang does not disclose a wordline (WL) transistor formed in the first region and coupled to the Flash memory cell gate stack, the WL transistor including a WL gate formed over a third gate oxide layer exclusive of nitridation. However, Chuang discloses (see, for example, FIG. 1) an integrated circuit comprising a word-line transistor 122 coupled to a flash memory cell gate stack 110, the WL transistor including a WL gate 122A/122B formed over a third gate oxide layer 112 exclusive of nitridation. In paragraph [0013], Chuang disclose the third gate oxide layer 112 includes an oxide. It would have been obvious to one of ordinary skill in the art to have a word-line (WL) transistor formed in the first region and coupled to the Flash memory cell gate stack, the WL transistor including a WL gate formed over a third gate oxide layer exclusive of nitridation in order to enable easy access to the memory cell, and eliminate the charge-depletion problem.
Regarding claim 5, see, for example, FIG. 1 wherein Chuang discloses a gate 216 of a first transistors 210 and the WL gate 122A of the WL transistor 122 being formed from a common gate layer. Also see 112 rejection above.
Regarding claim 6, Chang in view of Chuang does not disclose the common gate layer having a thickness of about 300 A to 1000 A; however, it would have been obvious to one of ordinary skill in the art to have the common gate layer have a thickness of about 300 A to 1000 A in order to ensure structural integrity with low electric resistance, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 7, Chang in view of Chuang does not disclose the third gate oxide layer having a thickness of about 15 A to 35 A; however, it would have been obvious to one of ordinary skill in the art to have disclose the third gate oxide layer having a thickness of about 15 A to 35 A in order to have high switching speeds with minimal leakage, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 8, Chang in view of Chuang does not disclose each set of the second transistors includes a gate having a thickness of about 600 Å that overlies the second gate oxide layer; however, it would have been obvious to one of ordinary skill in the art to have each set of the second transistors includes a gate having a thickness of about 600 Å that overlies the second gate oxide layer in order to have structural robustness with low electrical resistance, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 9, see, for example, FIG. 8 wherein Chang discloses the first gate 126b the second gate 126c being formed from different gate layers.
Regarding claim 14, Chang in view of Chuang does not explicitly state the first voltage level being greater than or equal to 4V, such as 5V; and the second voltage levels being less than 4V, such as 3.3V, 1.8V, 1.5V, or 1.0V; however, it would have been obvious to one of ordinary skill in the art to have the first voltage level being greater than or equal to 4V, such as 5V; and the second voltage levels being less than 4V, such as 3.3V, 1.8V, 1.5V, or 1.0V in order to implement transistors that require different voltage levels such as peripheral devices and/or logic devices in more robust electronic devices according to the preferences of the user.
Claim(s) 10 thru 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. US 2016/0042957 A1 as applied to claims 1-3 above, and further in view of Yi et al. US 2017/0110469 A1. Chang does not disclose the first region comprises a recessed area having a depth of about 1000 Å to 1200 Å from the second gate oxide layers, and wherein the Flash memory cell gate stack and the first transistor are formed in the recessed area. However, Yi discloses (see, for example, FIG. 1, and 2B) an integrated circuit 10 comprising a recessed area 100r, and flash memory cell gate stack 2201 and first transistor 2201 being formed in the recessed area. In paragraph [0024], Yi discloses the recessed area 100r having a depth D1 of being larger than or equal to 1000 A. It would have been obvious to one of ordinary skill in the art to have the first region comprises a recessed area having a depth of about 1000 Å to 1200 Å from the second gate oxide layers, and wherein the Flash memory cell gate stack and the first transistor are formed in the recessed area in order to improve memory density while facilitating high speed in the non-recessed region, and overall circuit.
Regarding claim 11, see, for example, FIG. 1 and paragraph [0024] wherein Yi discloses the first region comprises a first recessed area and a second recessed area being different than the first recessed area, the first and second recessed areas having a depth of about 1000 Å to 1200 Å from the second gate oxide layers; the flash memory cell gate stack 2201 being located in the first recessed area; and the first transistor 2201 being located in the second recessed area.
Regarding claims 12-13, see, for example, FIG. 1 wherein Yi discloses a top surface of the Flash memory cell/first transistor 2201 being substantially coplanar with the second gate oxide layer 291.
Regarding claim 14, Chang in view of Yi does not explicitly state the first voltage level being greater than or equal to 4V, such as 5V; and the second voltage levels being less than 4V, such as 3.3V, 1.8V, 1.5V, or 1.0V; however, it would have been obvious to one of ordinary skill in the art to have the first voltage level being greater than or equal to 4V, such as 5V; and the second voltage levels being less than 4V, such as 3.3V, 1.8V, 1.5V, or 1.0V in order to implement transistors that require different voltage levels such as peripheral devices and/or logic devices in more robust electronic devices according to the preferences of the user.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. US 2016/0042957 A1 as applied to claims 1-3 above, and further in view of Riley et al. US 2015/0031178 A1. Chang does not disclose at least one set of the one or more sets of second transistors includes a silicon-germanium (SiGe) layer. However, Riley discloses (see, for example, FIG. 1H) an integrated circuit comprising transistors 106/104 having silicon germanium layers 166/168 respectively. It would have been obvious to one of ordinary skill in the art to have at least one set of the one or more sets of second transistors includes a silicon-germanium (SiGe) layer in order to improve speed and driving current while lowering contact resistance. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
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Eugene Lee
January 13, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815