DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 11, 32, 33, 36, 37, and 40 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. US 2022/0052059 A1. Wang discloses (see, for example, FIG. 36A-36C) an integrated circuit (IC), comprising: a substrate 10 including a first region MC Area 2/HV Area 4 and a second region Logic Area 6; a memory cell gate stack S1/S2 disposed in the first region MC Area 2/HV Area 4; a first transistor HV Area 4 formed disposed in the first region MC Area 2/HV Area 4 and operable at a first voltage level, the first transistor HV Area 4 including a gate 48 formed disposed over a first gate oxide layer 38 exclusive of nitridation; and one or more sets of second transistors LS1/LS2 disposed in the second region Logic Area 6, each set operable at a corresponding second voltage level different than the first voltage level and including a corresponding second gate oxide layer 56; wherein the first region MC Area 2/HV Area 4 comprises a recessed area of the substrate with the memory cell gate stack S1/S2 and the first transistor HV AREA 4 disposed in the recessed area of the substrate 10. In FIG. 1A-1C, Wang discloses the first region MC Area 2/HV Area 4 having a recessed area relative to the second region Logic Area 6.
Regarding claims 4, and 36, see, for example, FIG. 15 wherein Wang discloses a
wordline transistor including a wordline gate 48a disposed over a third gate oxide layer 46.
Regarding claims 5, and 37 see, for example, FIG. 9A-9C wherein Wang discloses common gate layer 48.
Regarding claim 11, see, for example, FIG. 36A-36C wherein Wang discloses the first region MC Area 2/HV Area 4 having a first recessed area MC Area 2 and second recessed area HV Area 4 wherein the second recessed area HV Area 4 contains a first transistor as shown in FIG. 36B.
Regarding claims 32, and 33, see, for example, paragraph [0046] wherein Wang discloses the first gate oxide layer 38 may include oxide, and in paragraph [0050, Wang discloses the second gate oxide layer 56 includes silicon oxynitride.
Regarding claim 40, see, for example, FIG. 36A-36C wherein Wang discloses the gate 48 of the first transistor and the gate 48 of the second transistors comprise different gate layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, 6 thru 10, 14, 34, 35, 38, 39, 41, and 42 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. US 2022/02252059 A1 as applied to claims 1, 4, 5, 11, 32, 33, 36, 37, and 40. Wang does not specifically disclose the first oxide layer having a thickness of about 160 to 200 A. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the first oxide layer having a thickness of about 160 to 180 A in order to have dielectric reliablity with minimal leakage, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 3, and 35, Wang does not specifically disclose the second oxide layer
having a thickness ranging from about 15 A to about 45 A based on the second voltage level; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the second oxide layer having a thickness ranging from about 15 A to about 45 A based on the second voltage level in order to have dielectric reliability with minimal leakage, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 6, Wang does not disclose the common gate layer having a thickness of about 300 A to 1000 A; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the common gate layer have a thickness of about 300 A to 1000 A in order to ensure structural integrity with low electric resistance, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claims 7, and 38, Wang does not disclose the third gate oxide layer having a thickness of about 15 A to 35 A; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the third gate oxide layer having a thickness of about 15 A to 35 A in order to have high switching speeds with minimal leakage, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 8, and 39, Wang does not disclose each set of the one or more sets of second transistors includes a gate having a thickness of about 600 Å that overlies the second gate oxide layer; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have each set of the one or more sets of the second transistors includes a gate having a thickness of about 600 Å that overlies the second gate oxide layer in order to have structural robustness with low electrical resistance, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claims 9, and 40, see, for example, FIG. 36A-36C wherein Wang discloses the gate 48 of the first transistor and the gate 48 of the second transistors comprise different gate layers.
Regarding claims 10, and 41, Wang does not specifically disclose the recessed area has a depth of about 1000 A to 1200 A from the second gate oxide layers of the second transistor; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date to have the recessed area has a depth of about 1000 A to 1200 A from the second gate oxide layers of the second transistor in order to prevent current crowding at the surface of the substrate, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claims 14, and 42, Wang does not explicitly state the first voltage level being greater than or equal to 4V, such as 5V; and the second voltage levels being less than 4V, such as 3.3V, 1.8V, 1.5V, or 1.0V; however, it would have been obvious to one of ordinary skill in the art to have the first voltage level being greater than or equal to 4V, such as 5V; and the second voltage levels being less than 4V, such as 3.3V, 1.8V, 1.5V, or 1.0V in order to implement transistors that require different voltage levels such as peripheral devices and/or logic devices in more robust electronic devices according to the preferences of the user.
Regarding claim 34, see the rejection for claim 2 above.
Claim(s) 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. US 2022/02252059 A1 as applied to claims 1, 4, 5, 11, 32, 33, 36, 37, and 40, and further in view of Yi et al. US 2017/0110469 A1. Wang does not disclose a top surface of the memory cell gate stack being substantially coplanar with the second gate oxide layer. However, Yi discloses (see, for example, FIG. 1) a top surface of the Flash memory cell/first transistor 2201 being substantially coplanar with the second gate oxide layer 291. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date to have a top surface of the memory cell gate stack being substantially coplanar with the second gate oxide layer in order to improve memory density while maintaining a reference plane for minimizing recess defects.
Regarding claim 13, see the rejection for claim 12 above.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. US 2022/02252059 A1 as applied to claims 1, 4, 5, 11, 32, 33, 36, 37, and 40 above, and further in view of Riley et al. US 2015/0031178 A1. Wang does not disclose at least one set of the one or more sets of second transistors includes a silicon-germanium (SiGe) layer. However, Riley discloses (see, for example, FIG. 1H) an integrated circuit comprising transistors 106/104 having silicon germanium layers 166/168 respectively. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have at least one set of the one or more sets of second transistors includes a silicon-germanium (SiGe) layer in order to improve speed and driving current while lowering contact resistance. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15, and 32-42 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Eugene Lee
July 28, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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