Prosecution Insights
Last updated: August 17, 2026
Application No. 18/458,196

SEMICONDUCTOR DEVICE

Final Rejection §103§112
Filed
Aug 30, 2023
Priority
Dec 09, 2022 — JP 2022-197296
Examiner
MCDONALD, JASON ANDREW
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
KIOXIA Corporation
OA Round
2 (Final)
67%
Grant Probability
Favorable
3-4
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
4 granted / 6 resolved
-1.3% vs TC avg
Strong +100% interview lift
Without
With
+100.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
46 currently pending
Career history
62
Total Applications
across all art units

Statute-Specific Performance

§103
60.3%
+20.3% vs TC avg
§102
22.8%
-17.2% vs TC avg
§112
16.5%
-23.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 6 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Status The examiner acknowledges the amendments to claim 1. Claims 5-6, 8, 10, and 12-20 were previously withdrawn. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-4, 7, 9, and 11 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 1 includes a limitation “...one or more first films that are stacked alternately with the one or more first insulators in the first direction”. The specification defines a “first film” as either insulating [0043] or conductive [0082]. Claim 1 does not make clear which is intended. Claims 2-4, 7, 9, and 11 are rejected for their dependency on claim 1. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al (US 20190067314 A1, hereinafter “Lu”), in view of Hwang et al (US 20200219808 A1, hereinafter “Hwang”). Regarding Claim 1 – Lu discloses a semiconductor device comprising: a substrate (202 [0042] and Fig. 2); a first stacked film provided above the substrate (210 [0054] and Fig. 2), including a plurality of electrode layers (206 [0046] and Fig. 2) and a plurality of first insulators (208 [0046] and Fig. 2) that are alternately stacked in a first direction (Y in Fig. 2), and included in a memory cell array ([0036]); a second stacked film provided above the substrate (214 [0054] and Fig. 2), including one or more first insulators of the plurality of first insulators (232 same as 208 [0054] and Fig. 2), and one or more first films (234 [0054] and Fig. 2) that are stacked alternately with the one or more first insulators in the first direction (Y in Fig. 2); a first plug provided in the second stacked film (through array contact (TAC) 236 [0056] and Fig. 2); and a first interconnect layer provided on the first plug (Interconnect 246 comprising 250 and 252 [0060], [0063], and Fig. 2), and being in contact with the first plug (connected to 218 and 236 as in Fig. 2), wherein the first interconnect layer is in contact with an upper end of the first plug. Lu fails to disclose the first interconnect layer is in contact with a side face of the first plug in a vicinity of the upper end of the first plug. However, Hwang discloses the first interconnect layer (420, Hwang [0055] and Fig. 6) is in contact with a side face of the first plug (222, Hwang Fig. 6) in a vicinity of the upper end of the first plug (Hwang [0055] and Fig. 6). Hwang discloses an analogous connection to Lu between a via plug and an interconnect layer. Hwang teaches a via plug may be formed in a pillar shape and protrude above the lower surface of the interconnect layer for the benefit of increasing the contact area between the interconnect layer and the via plug (Hwang [0055]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Lu and Hwang to form a via plug in a pillar shape to protrude above the lower surface of the interconnect layer for the benefit of increasing the contact area between the interconnect layer and the via plug. PNG media_image1.png 394 562 media_image1.png Greyscale PNG media_image2.png 548 429 media_image2.png Greyscale Regarding Claim 2 – Lu modified by Hwang discloses all the limitations of Claim 1. The combination of Lu and Hwang further discloses the first stacked film including the plurality of electrode layers and the plurality of first insulators (Lu [0046] and Fig. 2); a columnar portion provided in the first stacked film (NAND strings 204, Lu [0046] and Fig. 2), extending in the first direction (Y in Lu Fig. 2), and including a semiconductor layer (220, Lu [0048]); and a second interconnect layer provided on the first stacked film (NAND string contacts 238, Lu [0058] and Fig. 2), and electrically connected to the columnar portion (Lu Fig. 2), and the first interconnect layer is provided on the second interconnect layer and the first plug (246 on 238 and 236 in Lu Fig. 2), and is electrically connected to the second interconnect layer and the first plug (Lu Fig. 2). Regarding Claim 3 – Lu modified by Hwang discloses all the limitations of Claim 1. The combination of Lu and Hwang further discloses the one or more first films are one or more second insulators formed of an insulating material that is different from an insulating material of the one or more first insulators (One of these layers can be silicon nitride and the other silicon oxide, Lu [0065] and [0074]). Regarding Claim 4 – Lu modified by Hwang discloses all the limitations of Claim 3. The combination of Lu and Hwang further discloses the one or more first insulators include silicon and oxygen (232 silicon oxide, Lu [0074]), and the one or more second insulators include silicon and nitrogen (234 silicon nitride, Lu [0074]). Regarding Claim 7 – Lu modified by Hwang discloses all the limitations of Claim 1. The combination of Lu and Hwang further discloses the plurality of electrode layers and the one or more first films do not include an electrode layer and a first film that are in contact with each other (Barrier structure 235 separates them, Lu [0055] and Fig. 2, which is also barrier structure 124 in, Lu [0055] and Fig. 1A). PNG media_image3.png 422 551 media_image3.png Greyscale Regarding Claim 9 – Lu modified by Hwang discloses all the limitations of Claim 1. The combination of Lu and Hwang further discloses a plurality of second plugs respectively electrically connected to the plurality of electrode layers (Word line contacts 242, Lu [0058] and Fig. 2). Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lu et al (US 20190067314 A1, hereinafter “Lu”), in view of Hwang et al (US 20200219808 A1, hereinafter “Hwang”), and further in view of Park et al (US 20140306279 A1, hereinafter “Park”). Regarding Claim 11 – Lu modified by Hwang discloses all the limitations of Claim 9. The combination of Lu and Hwang fails to disclose the plurality of second plugs are provided in the first stacked film via a plurality of fourth insulators that are respectively provided on side faces of the plurality of second plugs. However, Park discloses the plurality of second plugs are provided in the first stacked film via a plurality of fourth insulators that are respectively provided on side faces of the plurality of second plugs (Insulating spacers 170 [0060] and Fig. 21). Park discloses a three-dimensional memory device similar to Lu. Park teaches lining the second plugs with insulating spacers to separate the associated plugs from the adjacent word lines they pass through (Park [0009] and Fig. 21). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Lu and Park to line the second plugs with insulating spacers to separate the plugs from adjacent word lines. PNG media_image4.png 454 644 media_image4.png Greyscale Response to Arguments Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Aug 30, 2023
Application Filed
Feb 13, 2026
Non-Final Rejection mailed — §103, §112
May 13, 2026
Response Filed
Jul 15, 2026
Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12697688
SEMICONDUCTOR DEVICE MANUFACTURING DEVICE AND MANUFACTURING METHOD
3y 5m to grant Granted Aug 04, 2026
Patent 12666616
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 5m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 2 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
67%
Grant Probability
99%
With Interview (+100.0%)
3y 6m (~6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 6 resolved cases by this examiner. Grant probability derived from career allowance rate.

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