DETAILED ACTION
This Office action responds to Applicant’s election filed on 01/07/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The Applicant’s response on 01/07/2026 in reply to the restriction mailed on 11/07/2025 has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-27.
Election/Restriction
The Applicant’s response on 01/07/2026 in reply to the restriction/election requirements mailed on 11/07/2025 has been entered. Applicant’s election of Group I (claims 1-14, and 21-27) drawn to a package substrate and an integrated circuit package) is acknowledged. However, in light of the Applicant’s amendment of the independent method claim 15, the Group (device-method) restriction is moot, because there is no more demonstrated distinctiveness between the device claim 1 and method claim 15. Thus, the Group (device-method) restriction is withdrawn and Group II (claims 15-20) are considered for further prosecution.
Applicant’s election of Species 1 corresponding to figs. 1A-1E, is acknowledged. Applicant considers that claims 1-7, 9-23, and 25-28 should be considered for further prosecution. Examiner agrees. Claims 8, 16-20, 24, and 28 are withdrawn by corresponding to non-elected species. Because the Applicant did not point out any errors in the species restriction, the species restriction mailed on 11/07/2025 is considered without traverse.
Claims 8, 16-20, 24, and 28 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/07/2026.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Specification Objection
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Drawings Objections
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the a plurality of first vias (in the first region, which is the central region under the dies) coupling a first metal interconnect 122(1)(1) of the plurality of first metal interconnects 122(1)(1) to a third metal interconnect of the plurality of third metal interconnects (third interconnects are in the first region of the first film metallization layer 106(1)), recited in claim 2, must be shown the drawings or the feature(s) canceled from the claim(s).
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. The first PPG substrate 112(1) (denoted with “PPG substrate 112(1)” in fig. 1) that coincide with the first metallization layer 106(1) and shown as a different layer then in the element 112(1) (from the right side of fig. 1), recited in claim 2, must be shown the drawings or the feature(s) canceled from the claim(s).
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. The metal pillars from the core layer 117 coupled to a first metal interconnect 122(1)(1) of the plurality of first metal interconnects 122(1)(1), and to a third metal interconnect of the plurality of third metal interconnects, as recited in claim 7, must be shown the drawings or the feature(s) canceled from the claim(s).
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because:
reference character 112(1) from fig. 1 has been used to designate both a first PPG substrate (see the left side of fig. 1) and the first metallization layer, which should be marked instead with 106(1) (see the right side of fig. 1)
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5 and 7 are rejected under 35 U.S.C. 112(b) as being indefinite.
The claim is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint regard as the invention.
Claim 5 (and any dependents) recites the limitation "the second PPG metallization layer comprising a third surface … and a third metal layer, comprising a plurality of third metal interconnects exposed from the third surface:”. The claim defines a “third surface”, a “third metal layer”, and a “third metal interconnects”. Because the second PPG metallization layer is 114(2) in the second substrate, far down from the first PPG metallization layer 114(1) that is in the first substrate, the “third surface”, a “third metal layer”, and a “third metal interconnects” from claim 5 are not the same as the “third surface”, a “third metal layer”, and a “third metal interconnects” from claim 2. Examiner believe that the “third surface”, a “third metal layer”, and a “third metal interconnects” from claim 5 should be changes with “fourth surface”, a “fourth metal layer”, and a “fourth metal interconnects”, because there are different surfaces. For the purposes of examination to apply prior art, this was treated as the “fourth surface”, a “fourth metal layer”, and a “fourth metal interconnects” in a second substrate.
Claim 7 (and any dependents) also recites the limitation "… the core layer comprising a plurality of a plurality of metal pillars each coupled to a first metal interconnect of the plurality of first metal interconnects, and to a third metal interconnect of the plurality of third metal interconnects”. It is not clear from this claim how the metal pillars couple to a first metal interconnect of the plurality of first metal interconnects, and to a third metal interconnect of the plurality of third metal interconnects, when a first metal interconnect of the plurality of first metal interconnects, and to a third metal interconnect of the plurality of third metal interconnects are on the same side of the core layer. The Examiner believes that instead of “third metal interconnect”, it should be “fourth metal interconnect” which is on the other side of the core layer. However, even if it is considered a” fourth metal interconnect”, figs. 1 and 2 do not show that the metal pillars connect with the first metal interconnects and the fourth metal interconnects. Examiner requests clarifications and also a change in the wording of these limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-5, 7, 9, and 14-15 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon (US 2021/0127484) in view of Kim (US 2024/0079393).
Regarding claim 1, Yoon shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) most aspects of the instant invention including a package substrate 100A or 150/131/110/121/140, comprising a first substrate, comprising:
A first metallization layer 121/122 comprising a first surface and extending in a first direction
The first metallization layer 121/122 comprising:
A first film insulating layer 121
A first metal layer 122 comprising:
A plurality of first metal interconnects 122 exposed from the first surface in a first region of the first film metallization layer 121/122
A plurality of second metal interconnects 122 exposed from the first surface in a second region of the first film metallization layer 121/122
A second substrate comprising:
A first dielectric metallization layer 121/122 adjacent to the first surface in the second region
The first dielectric metallization layer 121/122 comprising:
A second surface
A second insulating layer 121
A second metal layer 122 comprising a plurality of first metal pads 122w exposed from the second surface
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However, Yoon fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show that the first dielectric metallization layer 121/122 is a pre-impregnated (PPG) metallization layer that comprises a PPG material. Yoon shows that the first dielectric metallization layer 121/122w is a metallization layer comprising a dielectric layer 121 (see, e.g., Yoon: par. [0031]). Kim, in a similar device to Yoon, shows (see, e.g., Kim: fig. 1) that the dielectric metallization layer 314H comprises prepreg or pre-impregnated (PPG) material (see, e.g., Kim: par. [0040]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the dielectric metallization layer of Yoon or the PPG metallization layer of Kim because these were recognized in the semiconductor art for their use as metallization layers in semiconductor device packages, as taught by Yoon and by Kim, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 2, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) that the first substrate further comprises:
A second film metallization layer 121/122 adjacent to the first film metallization layer 121/122 and extending in the first direction
The second film metallization layer 121/122 comprising:
A third surface
A second film insulating layer 121
A third metal layer 122 comprising:
A plurality of third metal interconnects 122w exposed from the third surface
A plurality of fourth metal interconnects 122w exposed from the third surface
The first film metallization layer 121/122 further comprising:
A plurality of first vias 123w each coupling a first metal interconnect 122w of the plurality of first metal interconnects 122w to a third metal interconnect 122w of the plurality of third metal interconnects 122w
A plurality of second vias 123w each coupling a second metal interconnect 122w of the plurality of second metal interconnects 122w to a fourth metal interconnect 122w of the plurality of fourth metal interconnects 122w
Regarding claim 4, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) that the second substrate further comprises a plurality of first vias 123w each coupling a first metal pad 122w of the plurality of first metal pads 122w to a second metal interconnect 122w of the plurality of second metal interconnects 122w.
Regarding claim 5, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) that the second substrate further comprises a second dielectric metallization layer in the second region and adjacent to the first PPG metallization layer on an opposite side of the first PPG metallization layer. Even if Yoon fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show that the first dielectric metallization layer 121/122 is a pre-impregnated (PPG) metallization layer that comprises a PPG material. Yoon shows that the first dielectric metallization layer 131/132 is a metallization layer comprising a dielectric layer 131 (see, e.g., Yoon: par. [0031]), then Kim, in a similar device to Yoon, shows (see, e.g., Kim: fig. 1) that the dielectric metallization layer 314H comprises prepreg or pre-impregnated (PPG) material (see, e.g., Kim: par. [0040]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the dielectric metallization layer of Yoon or the PPG metallization layer of Kim because these were recognized in the semiconductor art for their use as metallization layers in semiconductor device packages, as taught by Yoon and Kim, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Thus, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) that the second substrate further comprises a second PPG metallization layer 131/132 in the second region and adjacent to the first PPG metallization layer 122/122 on an opposite side of the first PPG metallization layer 122/122.
Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) that the second PPG metallization layer 131/132 comprising:
A third surface
A third PPG insulating layer 131 comprising PPG material
A third metal layer 132 comprising a plurality of third metal interconnects 132w exposed from the third surface
The first PPG metallization layer 121/122 further comprises:
A plurality of first vias 123w each coupling a first metal pad 122w of the plurality of first metal pads 122w to a third metal interconnect 122w of the plurality of third metal interconnects 122w
The second PPG metallization layer 131/132 further comprises a plurality of second vias 133w each coupling a third metal interconnect 132w of the plurality of third metal interconnects 132w to a second metal interconnect 132w of the plurality of second metal interconnect.
Regarding claim 7, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) a third substrate comprising:
A second film metallization layer 121/122 adjacent to the first film metallization layer and extending in the first direction
The second film metallization layer 121/122 comprising:
A third surface
A second film insulating layer 121
A third metal layer 122, comprising:
A plurality of third metal interconnects 122w exposed from the third surface
A plurality of fourth metal interconnects 122w exposed from the third surface
A core layer 110 between the first substrate and the third substrate in a second direction orthogonal to the first direction
The core layer 110 comprising:
A plurality of metal pillars 115 each coupled to a first metal interconnect 122w of the plurality of first metal interconnects 122w, and to a third metal interconnect 132w of the plurality of third metal interconnects 132w
Regarding claim 9, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) that the first film insulating layer 121 comprises a polyimide (see, e.g., Yoon: par. [0038]).
Regarding claim 14, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) that the device is selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone 1100; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
Regarding claim 15, Yoon shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) most aspects of the instant invention including a package substrate 100A or 150/131/110/121/140, comprising forming a first substrate, comprising:
Forming a first metallization layer 121/122 comprising a first surface and extending in a first direction
Forming a first metallization layer 121/122 comprising:
Forming a first film insulating layer 121
Forming a first metal layer 122 comprising:
Forming a plurality of first metal interconnects 122 exposed from the first surface in a first region of the first film metallization layer 121/122
Forming a plurality of second metal interconnects 122 exposed from the first surface in a second region of the first film metallization layer 121/122
Forming a second substrate comprising:
Forming a first dielectric metallization layer 121/122 adjacent to the second surface in the second region
Forming first dielectric metallization layer 121/122 comprising:
Forming a second insulating layer 121
Forming a second metal layer 122
Forming a plurality of first metal pads 122w exposed from the second surface
However, Yoon fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show the method step of the first dielectric metallization layer 121/122 that is a pre-impregnated (PPG) metallization layer comprising a PPG material. Yoon shows that method step of the first dielectric metallization layer 121/122w that is a metallization layer comprising a dielectric layer 121 (see, e.g., Yoon: par. [0031]). Kim, in a similar method to Yoon, shows (see, e.g., Kim: fig. 1) that the dielectric metallization layer 314H comprises prepreg or pre-impregnated (PPG) material (see, e.g., Kim: par. [0040]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the dielectric metallization layer of Yoon or the PPG metallization layer of Kim because these were recognized in the semiconductor art for their use as metallization layers in semiconductor device packages, as taught by Yoon and by Kim, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon in view of Kim in further view of Dutta (US 2024/0347913).
Regarding claim 3, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) that most aspects of the instant invention, including metal interconnects 122.
However, Yoon in view of Kim fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show that the first pitch of first metal interconnects is less or equal to 5 µm. Dutta, in a similar device to Yoon in view of Kim, shows (see, e.g., Dutta: fig. 2B) that the pitch of metal interconnects 240(1) - 240(3) and 238(1) - 238(3) is less than 5 µm (see, e.g., Dutta: par. [0041]). Dutta further shows (see, e.g., Dutta: fig. 2B) that the metal interconnects 240(2), 240(3) are formed from a smaller L/S metal pattern and/or with a smaller pitch so that, for example, the device elements 208(1)-208(6) can be made of a smaller size to support smaller wavelengths or to support higher RF frequencies (see, e.g., Dutta: par. [0041]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a pitch of metal interconnect of Dutta in the device of Yoon in view of Kim, in order to fabricate the device elements of a smaller size to support smaller wavelengths or to support higher RF frequencies.
However, the differences in the pitches will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph below) of the mentioned pitches, and Dutta has identified such thicknesses as result-effective variables subject to optimization (see, e.g., Dutta: par. [0041]), it would have been obvious to one of ordinary skill in the art to use these pitch values in the device of Yoon in view of Kim.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed pitch values or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon in view of Kim in further view of Darmawikarta (US 2020/0051915).
Regarding claim 6, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) a layer 140 adjacent to the first PPG metallization layer 121/122.
Yoon in view of Kim fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show that this layer is a solder resist layer. Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) that the layer is a passivation ABF layer. Darmawikarta, in a similar device to Yoon in view of Kim, shows (see, e.g., Darmawikarta: fig. 2I) a solder resist layer 241. Darmawikarta further shows that the solder resist mask layer 241 is at a lateral surface of the multilayer substrate structure 105 and by removing portions of the solder resist mask layer 241 to form openings 242, 243, it results in exposing the substrate interconnect 106 and the bridge contact structure 235 by a HR lithographic process and/or HR exposure tool (for the exposure and development to open the solder resist openings) (see, e.g., Darmawikarta: par. [0070]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the solder resist layer of Darmawikarta or the passivation ABF layer of Yoon in view of Kim because these were recognized in the semiconductor art for their use as solder mask layers in semiconductor device packages, as taught by Darmawikarta and by Yoon and Kim, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Yoon in view of Kim in view of Darmawikarta shows (see, e.g., Yoon: fig. 3, and annotated fig. 3, and see, e.g., Darmawikarta: fig. 2I) that:
A solder resist layer 140 adjacent to the first PPG metallization layer 121/122 such that the first PPG metallization layer 121/122 is between the solder resist layer 140 and the first substrate in a second direction orthogonal to the first direction
The solder resist layer 140 comprising a plurality of openings
The plurality of first metal pads 122w each exposed from an opening of the plurality of openings
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon in view of Kim in further view of Oshima (US 2016/0234932).
Regarding claim 10, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) a first film insulating layer 121 and a second film insulating layer 121.
However, Yoon in view of Kim fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show that a ratio of a second thickness of the second insulating layer 121, in a second direction orthogonal to the first direction, to a first thickness of the first film insulating layer 121, in the second direction, is at least 1.5. Oshima, in a similar device to Yoon in view of Kim, shows (see, e.g., Oshima: fig. 13B) that the first insulator film 21 may have a thickness in a range of 1 μm to 100 μm (see, e.g., Oshima: par. [0037]), and the second insulator film 22 may have a thickness in a range of 15 μm to 200 μm (see, e.g., Oshima: par. [0039]). Thus, Oshima shows cases when the thickness ratios are at least 1.5. Oshima shows (see, e.g., Oshima: fig. 13B) that the thickness of the first insulating layer 21 and the thickness of the first insulating layer 22 are adjusted to control the CTE coefficient, and suppress the warping of the circuit board (see, e.g., Oshima: par. [0040]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the ratio of the thicknesses of the first and second insulating layers of Oshima in the device of Yoon in view of Kim, in order to control the CTE coefficient, and suppress the warping of the circuit board.
However, the differences in the ratio will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph 43) of the mentioned ratios, and Oshima has identified such ratios as result-effective variables subject to optimization (see, e.g., Oshima: par. [0040]), it would have been obvious to one of ordinary skill in the art to use these ratio values in the device of Yoon in view of Kim.
Regarding claim 11, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) a first film insulating layer 121 and a second film insulating layer 121.
However, Yoon in view of Kim fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show that the first film insulating layer 121 has a first thickness in a second direction orthogonal to the first direction between 10 μm and 35 μm, and the second insulating layer 121 has a second thickness in the second direction between 15 μm and 45 μm.
Oshima, in a similar device to Yoon in view of Kim, shows (see, e.g., Oshima: fig. 13B) that the first insulator film 21 may have a thickness in a range of 1 μm to 100 μm (see, e.g., Oshima: par. [0037]), and the second insulator film 22 may have a thickness in a range of 15 μm to 200 μm (see, e.g., Oshima: par. [0039]). Oshima shows (see, e.g., Oshima: fig. 13B) that the thickness of the first insulating layer 21 and the thickness of the first insulating layer 22 are adjusted to control the CTE coefficient, and suppress the warping of the circuit board (see, e.g., Oshima: par. [0040]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the thicknesses of the first and second insulating layers of Oshima in the device of Yoon in view of Kim, in order to control the CTE coefficient, and suppress the warping of the circuit board.
However, the differences in the thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph 43) of the mentioned thicknesses, and Oshima has identified such thicknesses as result-effective variables subject to optimization (see, e.g., Oshima: par. [0040]), it would have been obvious to one of ordinary skill in the art to use these thickness values in the device of Yoon in view of Kim.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon in view of Kim in further view of Byun (US 2008/0088037).
Regarding claim 12, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) a first film insulating layer 121 and a PPG metallization layer 121.
However, Yoon in view of Kim fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show that the first film insulating layer 121 has a first modulus of elasticity, and the first PPG metallization layer 121 has a second modulus of elasticity, wherein the second modulus of elasticity is greater than the first modulus of elasticity.
Byun, in a similar device to Yoon in view of Kim, shows (see, e.g., Byun: fig. 7) that the dielectric/insulating layer (as a PPG metallization layer) 234 has a second modulus of elasticity (ranging from approximately 5 GPa to approximately 10 GPa) and the dielectric/insulating layer (as the first film insulating) 233 has first modulus of elasticity (ranging between 300 MPa and 5GPa) (see, e.g., Byun: par. [0053]). Byun further shows that the modulus of elasticity for the dielectric/insulating layers are chosen in order to reduce the expansion of the insulators and reduce the tensile stress that can introduce defects into the interconnects (see, e.g., Byun: par. [0043]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the modulus of a second insulating layer of Byun greater than the modulus of a first insulating layer in the device of Yoon in view of Kim, in order to reduce the expansion of the insulators and reduce the tensile stress that can introduce defects into the interconnects.
However, the differences in the moduli will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph 43) of the mentioned moduli, and Byun has identified such moduli as result-effective variables subject to optimization (see, e.g., Byun: par. [0053]), it would have been obvious to one of ordinary skill in the art to use these modulus values in the device of Yoon in view of Kim.
Regarding claim 13, Yoon in view of Kim shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) a first film insulating layer 121 and a PPG metallization layer 121.
However, Yoon in view of Kim fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show that the first film insulating layer 121 has a first modulus of elasticity, and the first PPG metallization layer 121 has a second modulus of elasticity, wherein the first modulus of elasticity is between 5 GigaPascal (GPa) and 20 GPa, and the second modulus of elasticity between 14 GPa and 25 GPa.
Byun, in a similar device to Yoon in view of Kim, shows (see, e.g., Byun: fig. 7) that the dielectric/insulating layer (as a PPG metallization layer) 234 has a second modulus of elasticity (ranging from approximately 5 GPa to approximately 10 GPa) and the dielectric/insulating layer (as the first film insulating) 233 has first modulus of elasticity (ranging between 300 MPa and 5GPa) (see, e.g., Byun: par. [0053]). Byun further shows that the modulus of elasticity for the dielectric/insulating layers are chosen in order to reduce the expansion of the insulators and reduce the tensile stress that can introduce defects into the interconnects (see, e.g., Byun: par. [0043]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the moduli of a first and second insulating layers of Byun in the device of Yoon in view of Kim, in order to reduce the expansion of the insulators and reduce the tensile stress that can introduce defects into the interconnects.
However, the differences in the moduli will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph 43) of the mentioned moduli, and Byun has identified such moduli as result-effective variables subject to optimization (see, e.g., Byun: par. [0053]), it would have been obvious to one of ordinary skill in the art to use these modulus values in the device of Yoon in view of Kim.
Claims 21-23, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon (US 2021/0127484) in view of Kim (US 2024/0079393) in view of Lee (US 2022/0262777) in further view of Oh (US 2021/0066210).
Regarding claim 21, Yoon shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) most aspects of the instant invention including a package substrate 100A or 150/131/110/121/140, comprising a first substrate, comprising:
A first metallization layer 121/122 comprising a first surface and extending in a first direction
The first metallization layer 121/122 comprising:
A first film insulating layer 121
A first metal layer 122 comprising:
A plurality of first metal interconnects 122 exposed from the first surface in a first region of the first film metallization layer 121/122
A plurality of second metal interconnects 122 exposed from the first surface in a second region of the first film metallization layer 121/122
A second substrate comprising:
A first dielectric metallization layer 121/122 adjacent to the first surface in the second region
The first dielectric metallization layer 121/122 comprising:
A second surface
A second insulating layer 121
A second metal layer 122 comprising a plurality of first metal pads 122w exposed from the second surface
However, Yoon fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show that the first dielectric metallization layer 121/122 is a pre-impregnated (PPG) metallization layer that comprises a PPG material. Yoon shows that the first dielectric metallization layer 121/122w is a metallization layer comprising a dielectric layer 121 (see, e.g., Yoon: par. [0031]). Kim, in a similar device to Yoon, shows (see, e.g., Kim: fig. 1) that the dielectric metallization layer 314H comprises prepreg or pre-impregnated (PPG) material (see, e.g., Kim: par. [0040]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the dielectric metallization layer of Yoon or the PPG metallization layer of Kim because these were recognized in the semiconductor art for their use as metallization layers in semiconductor device packages, as taught by Yoon and by Kim, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Yoon in view of Kim fails (see, e.g., Yoon: fig. 3, and annotated fig. 3, and see, e.g., Kim: fig. 1) to show a first die comprising a plurality of die interconnects 160 each connected to a first metal interconnect 122w of the plurality of first metal interconnects 122w. Lee, in a similar device to Yoon in view of Kim, shows (see, e.g., Lee: fig. 1) shows a die 600 that has a plurality of die interconnects 650 each connected to a metal interconnect 520 of the plurality of metal interconnects 520. Lee further shows (see, e.g., Lee: fig. 1) that the die interconnects 650 electrically/directly connect the circuit layer of the device 600 to the intermediate pads 530 of the intermediate layer 550 (see, e.g., Lee: par. [0071]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a plurality of die interconnect of Lee each connected to a metal interconnect in the device of Yoon in view of Kim, in order to electrically/directly connect the circuit layer of the device to the intermediate pads of the intermediate layers.
However, Yoon in view of Kim in view of Lee fails (see, e.g., Yoon: fig. 3, and annotated fig. 3, and see, e.g., Kim: fig. 1) to show that a second die adjacent to the first die such that the first die is between the second die and the package substrate in a second direction orthogonal to the first direction. Oh, in a similar device to Yoon in view of Kim in view of Lee, shows (see, e.g., Oh: fig. 4) a second die 170 adjacent to the first die such that the first die 170 is between the second die 170 and the package substrate 120/111a/111b/130 in a second direction orthogonal to the first direction. Oh further shows (see, e.g., Oh: fig. 4) that a second die 170 adjacent to the first die such that the first die 170 is between the second die 170 and the package substrate 120/111a/111b/130 in a second direction orthogonal to the first direction, in order to include a stack memory die (see, e.g., Oh: par. [0058]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a second die adjacent to the first die such that the first die between the second die and the package substrate of Oh in the device of Yoon in view of Kim in view of Lee, in order to in order to include a stack memory die.
Yoon in view of Kim in view of Lee in view of Oh shows (see, e.g., Oh: fig. 4) a plurality of wire bonds 170W each connected to the second die 170 and a first metal pad 112b of the plurality of first metal pads 112b.
Regarding claim 22, Yoon in view of Kim in view of Lee in view of Oh shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) that the second substrate further comprises a plurality of first vias 123w each coupling a first metal pad 122w of the plurality of first metal pads 122w to a second metal interconnect 122w of the plurality of second metal interconnects 122w.
Regarding claim 23, Yoon in view of Kim in view of Lee in view of Oh shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) a third substrate comprising:
A second film metallization layer 121/122 adjacent to the first film metallization layer and extending in the first direction
The second film metallization layer 121/122 comprising:
A third surface
A second film insulating layer 121
A third metal layer 122, comprising:
A plurality of third metal interconnects 122w exposed from the third surface
A plurality of fourth metal interconnects 122w exposed from the third surface
A core layer 110 between the first substrate and the third substrate in a second direction orthogonal to the first direction
The core layer 110 comprising:
A plurality of metal pillars 115 each coupled to a first metal interconnect 122w of the plurality of first metal interconnects 122w, and to a third metal interconnect 132w of the plurality of third metal interconnects 132w
Regarding claim 27, Yoon in view of Kim in view of Lee in view of Oh shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) that the device is selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone 1100; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
Claims 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon in view of Kim in view of Lee in view of Oh in further view of Byun (US 2008/0088037).
Regarding claim 25, Yoon in view of Kim in view of Lee in view of Oh shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) a first film insulating layer 121 and a PPG metallization layer 121.
However, Yoon in view of Kim in view of Lee in view of Oh fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show that the first film insulating layer 121 has a first modulus of elasticity, and the first PPG metallization layer 121 has a second modulus of elasticity, wherein the second modulus of elasticity is greater than the first modulus of elasticity.
Byun, in a similar device to Yoon in view of Kim in view of Lee in view of Oh, shows (see, e.g., Byun: fig. 7) that the dielectric/insulating layer (as a PPG metallization layer) 234 has a second modulus of elasticity (ranging from approximately 5 GPa to approximately 10 GPa) and the dielectric/insulating layer (as the first film insulating) 233 has first modulus of elasticity (ranging between 300 MPa and 5GPa) (see, e.g., Byun: par. [0053]). Byun further shows that the modulus of elasticity for the dielectric/insulating layers are chosen in order to reduce the expansion of the insulators and reduce the tensile stress that can introduce defects into the interconnects (see, e.g., Byun: par. [0043]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the modulus of a second insulating layer of Byun greater than the modulus of a first insulating layer in the device of Yoon in view of Kim in view of Lee in view of Oh, in order to reduce the expansion of the insulators and reduce the tensile stress that can introduce defects into the interconnects.
However, the differences in the moduli will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph 43) of the mentioned moduli, and Byun has identified such moduli as result-effective variables subject to optimization (see, e.g., Byun: par. [0053]), it would have been obvious to one of ordinary skill in the art to use these modulus values in the device of Yoon in view of Kim in view of Lee in view of Oh.
Regarding claim 26, Yoon in view of Kim in view of Lee in view of Oh im shows (see, e.g., Yoon: fig. 3, and annotated fig. 3) a first film insulating layer 121 and a PPG metallization layer 121.
However, Yoon in view of Kim in view of Lee in view of Oh fails (see, e.g., Yoon: fig. 3, and annotated fig. 3) to show that the first film insulating layer 121 has a first modulus of elasticity, and the first PPG metallization layer 121 has a second modulus of elasticity, wherein the first modulus of elasticity is between 5 GigaPascal (GPa) and 20 GPa, and the second modulus of elasticity between 14 GPa and 25 GPa.
Byun, in a similar device to Yoon in view of Kim in view of Lee in view of Oh, shows (see, e.g., Byun: fig. 7) that the dielectric/insulating layer (as a PPG metallization layer) 234 has a second modulus of elasticity (ranging from approximately 5 GPa to approximately 10 GPa) and the dielectric/insulating layer (as the first film insulating) 233 has first modulus of elasticity (ranging between 300 MPa and 5GPa) (see, e.g., Byun: par. [0053]). Byun further shows that the modulus of elasticity for the dielectric/insulating layers are chosen in order to reduce the expansion of the insulators and reduce the tensile stress that can introduce defects into the interconnects (see, e.g., Byun: par. [0043]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the moduli of a first and second insulating layers of Byun in the device of Yoon in view of Kim in view of Lee in view of Oh, in order to reduce the expansion of the insulators and reduce the tensile stress that can introduce defects into the interconnects.
However, the differences in the moduli will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph 43) of the mentioned moduli, and Byun has identified such moduli as result-effective variables subject to optimization (see, e.g., Byun: par. [0053]), it would have been obvious to one of ordinary skill in the art to use these modulus values in the device of Yoon in view of Kim in view of Lee in view of Oh.
Conclusion
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814