DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 3, 6, 9, and 16 – 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/14/2026.
Allowable Subject Matter
Claims 7 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gouchi (US 2015/0103499 A1).
Regarding Claim 1, Gouchi (US 2015/0103499 A1) discloses a semiconductor storage device (Fig 1-2) comprising: a memory device (3; [0054]) including a memory chip ([0054]); a first substrate (81b) having a first main surface (upper surface of 81b) and a second main surface (surface of 81b towards 81a), the memory device (3) disposed on the first main surface (upper surface of 81b), the second main surface disposed on a side opposite to the first main surface; and a second substrate (81c) having a third main surface (lower surface of 81c) and a fourth main surface (upper surface of 81c), the third main surface facing the first main surface, the fourth main surface disposed on a side opposite to the third main surface, and having a hollow portion (C; [0051]) penetrating from the third main surface to the fourth main surface and a connector portion (7; [0085] 7 provides connection to another device) is disposed on an outer edge (outer edge of assembly in Fig 1), wherein the memory device (3) is disposed within the hollow portion.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 5, 8 and 10 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchioka (US 2002/0177335 A1) in view of Shih (US 2006/0098396 A1).
Regarding Claim 1, Tsuchioka (US 2002/0177335 A1) discloses a semiconductor storage device (Fig 1-4) comprising: a memory device (28; [0006,0052,0055,0062] “inside the casing 2, electronic components 7, such as an interface circuit, a controller, a baseband processing circuit, an IC such as a memory”) including a memory chip ([0006,0052,0055,0062]); a first substrate (25) having a first main surface (upper surface of 25) and a second main surface (lower surface of 25), the memory device (28) disposed on the first main surface (upper surface of 25), the second main surface disposed on a side opposite to the first main surface; and a second substrate (14) having a third main surface (lower surface of 14) and a fourth main surface (upper surface of 14), the third main surface (lower surface of 14) facing the first main surface (upper surface of 25), the fourth main surface disposed on a side opposite to the third main surface, and having a (hollow-like) portion (lower end portion of 14 as seen in Fig 4A is empty or a concave space) penetrating from the third main surface to the fourth main surface and a connector portion (portion or region of 14 about 16,32; [0012-0015]) is disposed on an outer edge (towards leftward edge in Fig 1), wherein the memory device (28) is disposed within the hollow portion (see Fig 2).
Tsuchioka does not explicitly disclose a “hollow” portion.
Shih (US 2006/009396 A1) teaches of a device (Fig 1A) (also in circuit technology) comprising: a device (126); a first substrate (104) having a first main surface (upper surface of 104) and a second main surface (lower surface of 104), the device (126) disposed on the first main surface (upper surface of 104), the second main surface disposed on a side opposite to the first main surface; and a second substrate (102) having a third main surface (lower surface of 102) and a fourth main surface (upper surface of 102), the third main surface (lower surface of 102) facing the first main surface (upper surface of 104), the fourth main surface disposed on a side opposite to the third main surface, and having a hollow ([0027-0029], Abstract) portion (112) penetrating from the third main surface to the fourth main surface and a connector portion (portion or region of 118; [0027]; Abstract) is disposed on an outer edge (towards leftward edge in Fig 1A), wherein the device (126) is disposed within the hollow portion (112).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as disclosed by Tsuchioka, comprising a hollow portion as taught by Shih, in order to reduce overall volume, reduce overall size, simplify circuit design, and allow circuits to circumvent the mounted device(Shih, [0003-0008,0017,0031-0032]).
Regarding Claim 2, Tsuchioka further discloses the semiconductor storage device (Fig 1-4) according to claim 1, further comprising: a casing (11,18,19) having a box shape having an opening at a side end (at left side end of 11 allowing 16 to be exposed), wherein the memory device (28), the first substrate (25), and the second substrate (14) are accommodated in an internal space (14,25,28 are within the space formed by 18,19,11) of the casing.
Regarding Claim 5, Tsuchioka further discloses the semiconductor storage device (Fig 1-4) according to claim 2, wherein a sum of a thickness of the first substrate (thickness of 25 as seen in Fig 2), a thickness of the second substrate (thickness of 14 as seen in Fig 2), and a thickness of the memory device (thickness of 28 as seen in Fig 2) is larger than a height of the internal space (height of 27 as seen in Fig 2), and a sum of the thickness of the first substrate (thickness of 25 as seen in Fig 2) and the thickness of the memory device (thickness of 28 on right side of Fig 2) is smaller than the height of the internal space (height of 27).
Regarding Claim 8, Tsuchioka further discloses the semiconductor storage device (Fig 1-4) according to claim 2, wherein a thickness of the memory device (28) is larger than (thickness of 28 as seen in Fig 2 is larger than the thickness of 14 in Fig 2) a thickness of the second substrate (14).
Regarding Claim 10, Tsuchioka further discloses the semiconductor storage device (Fig 1-4) according to claim 2, wherein the connector portion (portion or region about 16 or 32 is shown near a center in a height direction of 27) is positioned near a center in a height direction in the internal space.
Regarding Claim 11, Tsuchioka in view of Shih teaches the limitations of the preceding claim.
Tsuchioka does not disclose the semiconductor storage device according to claim 1, wherein a dimension in a longitudinal direction of the second substrate is larger than a dimension in a longitudinal direction of the first substrate.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Tsuchioka in view of Shih, wherein a dimension in a longitudinal direction of the second substrate is larger than a dimension in a longitudinal direction of the first substrate, in order to accommodate mounting of larger components, in order to provide greater support and strength to the assembly with a larger substrate, or to increase overall rigidity of the assembly, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, page 14 [0033], Applicant has not disclosed any criticality for the claimed limitations. See also MPEP 2144.
Regarding Claim 12, Tsuchioka further discloses the semiconductor storage device (Fig 1-4) according to claim 1, wherein the connector portion (portion or region about 16 or 32) is disposed at an edge portion (portion or region at left side of Fig 1) in a longitudinal direction (left-right direction of 14 in Fig 1-2) of the second substrate (14).
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Tsuchioka (US 2002/0177335 A1) in view of Shih (US 2006/0098396 A1) as applied to claim 1 above and further in view of Kuster (US 2012/0194990 A1).
Regarding Claim 4, Tsuchioka in view of Shih teaches the limitations of the preceding claim.
Tsuchioka further discloses the semiconductor storage device (Fig 1-4) according to claim 1, wherein the connector portion (about 16,32) supports a form factor (see Fig 1-4).
Though Tsuchioka shows a seemingly standard connection portion, Tsuchioka does not explicitly state a predetermined form factor standard.
Kuster (US 2012/0194990 A1) teaches of a connector portion (about 16,32) supports a predetermined form factor standard ([0033]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Tsuchioka in view of Shih, wherein the connector portion supports a predetermined form factor standard as taught by Kuster, in order to allow USB connections, allow conformation of mSATA or SATA or to provide functionality (Kuster, [0033]).
Claim(s) 13, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchioka (US 2002/0177335 A1) in view of Shih (US 2006/0098396 A1) as applied to claim 1 above and further in view of Han (US 2020/0022273 A1).
Regarding Claim 13, Tsuchioka in view of Shih teaches the limitations of the preceding claim.
Tsuchioka does not disclose the semiconductor storage device according to claim 1, wherein the memory device includes a plurality of memory chips, and the plurality of memory chips are stacked.
Han (US 2020/0022273 A1) teaches of a device (Fig 2) wherein a memory device (192,194) includes a plurality of memory chips (194a,194b,194c,194d; [0032-0035]), and the plurality of memory chips are stacked (see Fig 2).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Tsuchioka in view of Shih, wherein the memory device includes a plurality of memory chips, and the plurality of memory chips are stacked as taught by Han, in order to provide reliability, stability, and allow for a convenient means of storing large amounts of information (Han, [0002-0010]).
Regarding Claim 15,Tsuchioka in view of Shih teaches the limitations of the preceding claim.
Tsuchioka does not disclose the semiconductor storage device according to claim 1, wherein the memory device further includes a controller chip configured to control the memory chip.
Han (US 2020/0022273 A1) teaches of a device (Fig 2) wherein a memory device (192,194) further includes a controller chip (192) configured to control ([0032]) a memory chip (194).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Tsuchioka in view of Shih, wherein the memory device further includes a controller chip configured to control the memory chip as taught by Han, in order to provide reliability, stability, allow for a convenient means of storing large amounts of information, and provide control (Han, [0002-0010,0032-0035]).
Regarding Claim 20, Tsuchioka in view of Shih teaches the limitations of the preceding claim.
Tsuchioka does not disclose the semiconductor storage device according to claim 1, wherein the memory chip includes a NAND flash memory chip.
Han (US 2020/0022273 A1) teaches of a device (Fig 2) wherein a memory chip (194) includes a NAND flash memory chip ([0034]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Tsuchioka in view of Shih, wherein the memory chip includes a NAND flash memory chip as taught by Han, in order to provide reliability, stability, allow for a convenient means of storing large amounts of information, and provide control (Han, [0002-0010,0032-0035]).
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tsuchioka (US 2002/0177335 A1) in view of Shih (US 2006/0098396 A1) as applied to claim 1 above and further in view of Kim (US 2018/0160523 A1).
Regarding Claim 19, Tsuchioka in view of Shih teaches the limitations of the preceding claim.
Tsuchioka does not disclose the semiconductor storage device according to claim 1, wherein a semiconductor storage device includes a solid state drive.
Kim (US 2018/0160523 A1) teaches of a device (Fig 1-6) wherein a semiconductor storage device ([000,00226]) includes a solid state drive ([0022-0037]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Tsuchioka in view of Shih, wherein the semiconductor storage device includes a solid state drive as taught by Kim, in order to provide a non-volatile memory-based storage device, lower power consumption and provide relatively high storage density (Kim, [0002-0006,0022-0037]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Hiew (US 2009/0190277 A1) teaches of a semiconductor storage device (Fig 1-6) comprising: a memory device (150A; [0042]) including a memory chip ([0042]); a first substrate (110) having a first main surface and a second main surface, the memory device disposed on the first main surface, the second main surface disposed on a side opposite to the first main surface. This could be used in a 103 Rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2847
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