DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-13 in the reply filed on 01/16/2026 s acknowledged.
Claims 14-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/16/2026.
Claim Objections
Claims 1-13 are rejected to because of the following informalities:
Claim 1 recites “in the order of the first, second and third insulating films” which should be replaced with “in the order of a first insulating film of the plurality of first insulating films, a second insulating film of the plurality of second insulating films, and a third insulating film of the plurality of third insulating films”, to avoid antecedent basis issue.
Claim 1 recites “the first and second regions” which should be replaced with “the first region and the second region”, to avoid antecedent basis issue.
Claim 5 recites “each of the second insulating films” which should be replaced with “each of the plurality of second insulating films”, to avoid antecedent basis issue.
Claim 6 recites “each of the first insulating films” and “each of the second insulating films” which should be replaced with “each of the plurality of first insulating films” and “each of the plurality of second insulating films”, respectively, to avoid antecedent basis issue.
Claim 13 recites “the first and second regions” which should be replaced with “the first region and the second region”, to avoid antecedent basis issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 8 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0057444 to Park et al. (hereinafter Park).
With respect to claim 8, Park discloses a semiconductor memory device (e.g., memory cell array, see the annotated Fig. 5A below) (Park, Figs. 4, 5A-5B, ¶0004-¶0007, ¶0024-¶0025, ¶0032-¶0033, ¶0043-¶0082) comprising:
a multi-layered structure (e.g., 120/130 and 120/180) (Park, Figs. 4, 5A-5B, ¶0048, ¶0050-¶0051, ¶0054, ¶0060, ¶0065-¶0069, ¶0072) having a first region (e.g., a memory cell region including a first region A with vertically stacked gate electrodes 130) (Park, Figs. 4, 5A-5B, ¶0048, ¶0050-¶0051, ¶0054, ¶00600 and a second region (e.g., an end region B/C of the memory cell region and including an insulation region IR with vertically stacked insulating layers 120/180, wherein the gate electrodes 130 are absent) (Park, Figs. 4, 5A-5B, ¶0048, ¶0065-¶0069, ¶0072);
the first region (A) of the multi-layered structure comprising a first stack (e.g., 120/130) (Park, Figs. 4, 5A-5B, ¶0050, ¶0053-¶0054) and a first pillar (e.g., channel structure CH) (Park, Figs. 4, 5A-5B, ¶0060-¶0061);
the first stack (120/130) comprising an alternate stack in a first direction (e.g., a vertical Z-direction) (Park, Figs. 4, 5A-5B, ¶0050, ¶0054) of a plurality of first insulating films (120) containing oxygen (e.g., silicon oxide) (Park, Figs. 4, 5A-5B, ¶0054) and a plurality of first conductive films (130, gate electrodes) (Park, Figs. 4, 5A-5B, ¶0053);
the first pillar (CH) (Park, Figs. 4, 5A-5B, ¶0060-¶0061) comprising a first semiconductor layer (140) and extending in the first direction (e.g., Z-direction);
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the second region (e.g., the end region B/C of the region A and including through-wiring regions TB1/TB2) (Park, Figs. 4, 5A-5B, ¶0048, ¶0065-¶0066) of the multi-layered structure comprising a second stack (e.g., an insulation region IR including stacked interlayer insulating layers 120 and sacrificial insulating layers 180) (Park, Figs. 4, 5A-5B, ¶0067-¶0069) and a second pillar (e.g., DCH, dummy channel structure) (Park, Figs. 4, 5A-5B, ¶0072-¶0073);
the second stack (120/180) (Park, Figs. 4, 5A-5B, ¶0067) comprising an alternate stack in the first direction (e.g., the vertical Z-direction) of the plurality of first insulating films (120) containing oxygen (e.g., silicon oxide) (Park, Figs. 4, 5A-5B, ¶0054, ¶0069), and a plurality of second insulating films (e.g., sacrificial layers 180) containing nitrogen (e.g., silicon oxynitride) (Park, Figs. 4, 5A-5B, ¶0054, ¶0069, ¶0110) and oxygen;
the second pillar (e.g., DCH, dummy channel structures formed in second region including a through-wiring region TB1/TB2) (Park, Figs. 4, 5A-5B, ¶0072-¶0073, ¶0075) comprising a second semiconductor layer (140) and extending in the first direction (e.g., the vertical Z-direction);
the first (A) (Park, Figs. 4, 5A, ¶0048) and second (B/C) regions are adjacent each other in a second direction (e.g., X/Y-direction) intersecting the first direction (e.g., the Z-direction).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0057444 to Park in view of Cho (US 2020/0402998).
With respect to claim 1, Park discloses a semiconductor memory device (e.g., memory cell array, see the annotated Fig. 5A above) (Park, Figs. 4, 5A-5B, ¶0004-¶0007, ¶0024-¶0025, ¶0032-¶0033, ¶0043-¶0082) comprising:
a multi-layered structure (120/130 and 120/180) (Park, Figs. 4, 5A-5B, ¶0048, ¶0050-¶0051, ¶0054, ¶0060, ¶0065-¶0069, ¶0072) having a first region (e.g., a memory cell region including a first region A with vertically stacked gate electrodes 130) (Park, Figs. 4, 5A-5B, ¶0048, ¶0050-¶0051, ¶0054, ¶00600 and a second region (e.g., an end region B/C of the memory cell region and including an insulation region IR with vertically stacked insulating layers 120/180, wherein the gate electrodes 130 are absent) (Park, Figs. 4, 5A-5B, ¶0048, ¶0065-¶0069, ¶0072);
the first region (A) of the multi-layered structure comprising a first stack (e.g., 120/130) (Park, Figs. 4, 5A-5B, ¶0050, ¶0053-¶0054) and a first pillar (e.g., channel structure CH) (Park, Figs. 4, 5A-5B, ¶0060-¶0061);
the first stack (120/130) comprising an alternate stack in a first direction (e.g., a vertical Z-direction) (Park, Figs. 4, 5A-5B, ¶0050, ¶0054) of a plurality of first insulating films (120) containing oxygen (e.g., silicon oxide) (Park, Figs. 4, 5A-5B, ¶0054) and a plurality of first conductive films (130, gate electrodes) (Park, Figs. 4, 5A-5B, ¶0053);
the first pillar (CH) (Park, Figs. 4, 5A-5B, ¶0060-¶0061) comprising a first semiconductor layer (140) and extending in the first direction (e.g., Z-direction);
the second region (e.g., the end region B/C of the region A and including through-wiring regions TB1/TB2) (Park, Figs. 4, 5A-5B, ¶0048, ¶0065-¶0066) of the multi-layered structure comprising a second stack (e.g., an insulation region IR including stacked interlayer insulating layers 120 and sacrificial insulating layers 180) (Park, Figs. 4, 5A-5B, ¶0067-¶0069) and a second pillar (e.g., DCH, dummy channel structure) (Park, Figs. 4, 5A-5B, ¶0072-¶0073);
the second stack (120/180) (Park, Figs. 4, 5A-5B, ¶0067) comprising a repeated stack in the first direction (e.g., the vertical Z-direction) of the plurality of first insulating films (120) containing oxygen (e.g., silicon oxide) (Park, Figs. 4, 5A-5B, ¶0054, ¶0069), a plurality of second insulating films (e.g., sacrificial layers 180) containing nitrogen (e.g., silicon nitride) (Park, Figs. 4, 5A-5B, ¶0054, ¶0069, ¶0110), the repeated stack (120/180) being in the order of the first (120), second (180) insulating films,
the second pillar (e.g., DCH, dummy channel structures formed in second region including a through-wiring region TB1/TB2) (Park, Figs. 4, 5A-5B, ¶0072-¶0073, ¶0075) comprising a second semiconductor layer (140) and extending in the first direction (e.g., the vertical Z-direction);
the first (A) (Park, Figs. 4, 5A, ¶0048) and second (B/C) regions are adjacent each other in a second direction (e.g., X/Y-direction) intersecting the first direction (e.g., the Z-direction).
Further, Park does not specifically disclose a plurality of third insulating films containing nitrogen and at least one of oxygen and hydrogen, the repeated stack being in the order of the first, second and third insulating films.
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However, Cho teaches forming a vertical memory device (Cho, Figs. 2A, ¶0010, ¶0020-¶0053) comprising a stack of a plurality of first insulation layers (115) and a plurality of conductive layers (265) by replacing a plurality of sacrificial films (120) of a repeated stack (110/120, see the annotated Fig. 3 below) (Cho, Fig. 3, ¶0055-¶0062) including the plurality of first insulation films (110) containing oxygen (e.g., silicon oxide) (Cho, Fig. 3, ¶0055, ¶0058) and sacrificial layer structure (120). The sacrificial layer structure (120) (Cho, Fig. 3, ¶0055, ¶0058) includes a plurality of second insulating films (e.g., 120a, silicon nitride) (Cho, Fig. 3, ¶0061) containing nitrogen, and a plurality of third insulating films (e.g., 120b, silicon oxynitride) (Cho, Fig. 3, ¶0061) containing nitrogen and oxygen, the repeated stack being in the order of the first (110), second (120a) and third (120b) insulating films, to replace the sacrificial films with the gate electrode layers, and to provide a plurality of charge trapping patterns of the vertical memory device to improve electrical characteristics of the vertical memory device (Cho, ¶0010).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Park by forming a repeated stack including a plurality of sacrificial layers not replaced with the conductive layer in the second region having regularly locating dummy channel structures as taught by Park, wherein the plurality of sacrificial layers includes a plurality of third insulating films containing nitrogen and oxygen (e.g., SiON) having a different etching rate than a plurality of second insulating films containing nitrogen (e.g., SiN) as taught by Cho to have the semiconductor memory device, wherein a plurality of third insulating films containing nitrogen and oxygen, the repeated stack being in the order of the first, second and third insulating films, to provide a semiconductor memory device having improved reliability by regularly locating dummy channel structures in through-wiring regions including an insulation stack; and to provide a plurality of charge trapping patterns of the vertical memory device to improve electrical characteristics of the vertical memory device (Park, ¶0004, ¶0146; Cho, ¶0010, ¶0061).
Regarding claim 7, Park in view of Cho discloses the semiconductor memory device according to claim 1. Further, Park discloses the semiconductor memory device, further comprising: a first insulator (MS1) (Park, Figs. 4, 5A-5B, ¶0055, ¶0065-¶0066) penetrating through the first stack (120/130) in the first direction (e.g., Z-direction) and extending in a third direction (e.g., X-direction) intersecting the first direction (e.g., Z-direction) and the second direction (e.g., Y-direction), wherein the first insulator (MS1) isolating the first region (e.g., memory cell region A) and the second region (e.g., a region C in the end of the region A in the Y-direction and including through-wiring region TB2) from each other, and the first insulator (MS1) being between the first region (A) and the second region (C).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0057444 to Park in view of Cho (US 2020/0402998) as applied to claim 1, and further in view of Toriumi et al. (US 2009/0102027, hereinafter Toriumi).
Regarding claims 2 and 3, Park in view of Cho discloses the semiconductor memory device according to claim 1. Further, Park does not specifically disclose that an average hydrogen concentration of the plurality of third insulating films is more than 15 atom% (as claimed in claim 2); wherein an average oxygen concentration of the plurality of third insulating films is more than 5 atom% (as claimed in claim 3).
However, Toriumi teaches forming a repeating stack (102/104) (Toriumi, Figs. 1A-1C, ¶0005, ¶0008-¶0009, ¶0051-¶0053) comprising an insulator (102) including silicon nitride oxide containing oxygen, nitrogen, silicon, and hydrogen at concentrations (Toriumi, Figs. 1A-1C, ¶0052) ranging from 5 to 30 atom % and from 10 to 30 atom % for oxygen and hydrogen, respectively, to provide an insulation layer having a high dielectric strength voltage, a low dielectric constant for enabling high speed operation by reducing capacitance between the wirings, and a low hygroscopicity for preventing expansion of the insulating layer due to moisture absorption, and thus to provide a semiconductor device with high performance and reliability.
The claimed ranges overlap the ranges of prior art by Toriumi. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Park/Cho by forming a repeated stack including a plurality of silicon nitride oxide layers containing hydrogen and each having a specific composition as taught by Toriumi, wherein the plurality of silicon nitride oxide layers are formed as a plurality third insulating layers to have the semiconductor memory device, wherein an average hydrogen concentration of the plurality of third insulating films is more than 15 atom% (as claimed in claim 2); wherein an average oxygen concentration of the plurality of third insulating films is more than 5 atom% (as claimed in claim 3), in order to provide an insulation layer having a high dielectric strength voltage, a low dielectric constant for enabling high speed operation by reducing capacitance between the wirings, and a low hygroscopicity for preventing expansion of the insulating layer due to moisture absorption, and thus to provide a semiconductor device with high performance and reliability (Toriumi, ¶0005, ¶0008-¶0009, ¶0052).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0057444 to Park in view of Cho (US 2020/0402998) as applied to claim 1, and further in view of Cho (US 2009/0194809, hereinafter Cho’809).
Regarding claim 4, Park in view of Cho discloses the semiconductor memory device according to claim 1. Further, Park does not specifically disclose that a film thickness of each of the plurality of third insulating films is equal to or more than 1 nm.
However, Cho teaches forming the repeated stack (110/120) (Cho, Fig. 3, ¶0055-¶0062) including the sacrificial layer structure (120) (Cho, Fig. 3, ¶0055, ¶0058), wherein a thickness (Cho, Fig. 3, ¶00560 of each of the plurality of third insulating films (e.g., 120b, silicon oxynitride) (Cho, Fig. 3, ¶0061) is smaller than a thickness of each of the plurality of second insulating films (e.g., 120a, silicon nitride) (Cho, Fig. 3, ¶0061).
Further, Cho’809 teaches forming a silicon oxynitride layer (e.g., 3e/3c) (Cho’809, Fig. 1B, 2B, ¶0035, ¶0046-¶0049, ¶0066-¶0069) between the silicon nitride layer (3d) and the silicon oxide layer (3b/3f) and including a specific concentration of hydrogen, to block diffusion of free hydrogen into underlying/overlying silicon oxide layer, wherein a thickness of the silicon oxynitride layer (e.g., 3e/3c) is more than 0 nm and less than 3 nm. The claimed range overlaps the range of Cho’809.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Park/Cho by forming a repeated stack including a plurality of sacrificial layers having a plurality of silicon oxynitride films as taught by Cho, wherein each of the plurality of silicon oxynitride films includes hydrogen and having a thickness as taught by Cho’809 to have the semiconductor memory device, wherein a film thickness of each of the plurality of third insulating films is equal to or more than 1 nm, in order to provide the vertical memory device with improved electrical characteristics; and to block diffusion of free hydrogen into underlying/overlying silicon oxide layer (Cho, ¶0010, ¶0061; Cho’809, ¶0035, ¶0049, ¶0069).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0057444 to Park in view of Cho (US 2020/0402998) as applied to claim 1, and further in view of Han et al. (US 2019/0115365, hereinafter Han).
Regarding claims 5 and 6, Park in view of Cho discloses the semiconductor memory device according to claim 1. Further, Park does not specifically disclose that a film thickness of each of the plurality of first insulating films is equal to or less than 20 nm, and a film thickness of each of the second insulating films is equal to or less than 30 nm (as claimed in claim 5); wherein a film thickness of each of the first insulating films is equal to or more than 10 nm and equal to or less than 20 nm, and a film thickness of each of the second insulating films is equal to or more than 10 nm and equal to or less than 30 nm (as claimed in claim 6).
However, Han teaches forming a repeated stack (Han, Figs. 2, 6A, ¶0021-¶0032, ¶00, ¶0049) comprising a plurality of first insulating layers (e.g., 210, silicon oxide) (Han, Figs. 2, 6A, ¶0026) and a plurality of sacrificial layers (340) (Han, Figs. 2, 6A, ¶0035-¶0037, ¶0058) including a plurality of second sacrificial layer (602) and a plurality of third sacrificial layer (604), wherein a film thickness (208) (Han, Figs. 2, 6A, ¶0025) of each of the plurality of first insulating films (210) is between about 20 nm and 30 nm or less (that overlaps claimed ranges equal to or less than 20 nm, or equal to or more than 10 nm and equal to or less than 20 nm), to provide a thin isolator to reduce the overall height of the NAND string of the 3D memory device. Further, Han teaches that a film thickness of each of the second sacrificial films (602) (Han, Figs. 2, 6A, ¶0058) is about 10 nm that is in the claimed ranges of equal to or less than 30 nm, or equal to or more than 10 nm and equal to or less than 30 nm.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05); and a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Park/Cho by forming a repeated stack including a plurality of sacrificial layers and a plurality of first insulating layers having specific thicknesses as taught by Han, wherein the plurality of sacrificial layers includes a plurality of second insulating layers to have the semiconductor memory device, wherein a film thickness of each of the plurality of first insulating films is equal to or less than 20 nm, and a film thickness of each of the second insulating films is equal to or less than 30 nm (as claimed in claim 5); wherein a film thickness of each of the first insulating films is equal to or more than 10 nm and equal to or less than 20 nm, and a film thickness of each of the second insulating films is equal to or more than 10 nm and equal to or less than 30 nm (as claimed in claim 6), in order to provide thin isolators to reduce the overall height of the NAND string of the 3D memory device (Han, ¶0002, ¶0025, ¶0058, ¶0062).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0057444 to Park in view of Toriumi (US 2009/0102027).
Regarding claims 9-11, Park discloses the semiconductor memory device according to claim 8. Further, Park does not specifically disclose that an average hydrogen concentration of the plurality of second insulating films is more than 15 atom% (as claimed in claim 9); wherein an average oxygen concentration of the plurality of second insulating films is more than 17 atom% (as claimed in claim 10); wherein a total amount of hydrogen and oxygen of the plurality of second insulating films is more than 19 atom% (as claimed in claim 11).
However, Toriumi teaches forming a repeating stack (102/104) (Toriumi, Figs. 1A-1C, ¶0005, ¶0008-¶0009, ¶0051-¶0053) comprising an insulator (102) including silicon nitride oxide film containing oxygen, nitrogen, silicon, and hydrogen at concentrations (Toriumi, Figs. 1A-1C, ¶0052) ranging from 5 to 30 atom % and from 10 to 30 atom % for oxygen and hydrogen, respectively, such that a total amount of hydrogen and oxygen of the silicon nitride oxide film ranges from 15 to 60 atom%, in order to provide an insulation layer having a high dielectric strength voltage, a low dielectric constant for enabling high speed operation by reducing capacitance between the wirings, and a low hygroscopicity for preventing expansion of the insulating layer due to moisture absorption, and thus to provide a semiconductor device with high performance and reliability.
The claimed ranges overlap the ranges of prior art by Toriumi. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Park by forming an alternate stack including a plurality of silicon nitride oxide films containing hydrogen and each having a specific composition as taught by Toriumi, wherein the plurality of silicon nitride oxide layers containing hydrogen are formed as a plurality second insulating layers to have the semiconductor memory device, wherein an average hydrogen concentration of the plurality of second insulating films is more than 15 atom% (as claimed in claim 9); wherein an average oxygen concentration of the plurality of second insulating films is more than 17 atom% (as claimed in claim 10); wherein a total amount of hydrogen and oxygen of the plurality of second insulating films is more than 19 atom% (as claimed in claim 11), in order to provide an insulation layer having a high dielectric strength voltage, a low dielectric constant for enabling high speed operation by reducing capacitance between the wirings, and a low hygroscopicity for preventing expansion of the insulating layer due to moisture absorption, and thus to provide a semiconductor device with high performance and reliability (Toriumi, ¶0005, ¶0008-¶0009, ¶0052).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0057444 to Park in view of Han (US 2019/0115365).
Regarding claims 12 and 13, Park discloses the semiconductor memory device according to claim 8. Further, Park does not specifically disclose that a film thickness of each of the plurality of second insulating films is equal to or more than 10 nm (as claimed in claim 12); wherein a film thickness of each of the plurality of first insulating films is equal to or more than 10 nm and equal to or less than 40 nm (as claimed in claim 13).
However, Han teaches forming a repeated stack (Han, Figs. 2, 6A, ¶0021-¶0032, ¶00, ¶0049) comprising a plurality of first insulating layers (e.g., 210, silicon oxide) (Han, Figs. 2, 6A, ¶0026) and a plurality of sacrificial layers (340) (Han, Figs. 2, 6A, ¶0035-¶0037, ¶0058) including a plurality of second sacrificial layer (602) and a plurality of third sacrificial layer (604), wherein a film thickness (208) (Han, Figs. 2, 6A, ¶0025) of each of the plurality of first insulating films (210) is between about 20 nm and 30 nm (that is in the claimed range of equal to or more than 10 nm and equal to or less than 40 nm), to provide a thin isolator to reduce the overall height of the NAND string of the 3D memory device. Further, Han teaches that a film thickness of each of the second sacrificial films (602) (Han, Figs. 2, 6A, ¶0058) is about 10 nm that is in the claimed range of equal to or more than 10 nm.
Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Park by forming a repeated stack including a plurality of sacrificial layers and a plurality of first insulating layers having specific thicknesses as taught by Han, wherein the plurality of sacrificial layers includes a plurality of second insulating layers to have the semiconductor memory device, wherein a film thickness of each of the plurality of second insulating films is equal to or more than 10 nm (as claimed in claim 12); wherein a film thickness of each of the plurality of first insulating films is equal to or more than 10 nm and equal to or less than 40 nm (as claimed in claim 13), in order to provide thin isolators to reduce the overall height of the NAND string of the 3D memory device (Han, ¶0002, ¶0025, ¶0058, ¶0062).
Conclusion
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/NATALIA A GONDARENKO/ Primary Examiner, Art Unit 2891