DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-12) in the reply filed on January 5, 2026 is acknowledged.
Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on January 5, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang et al (US Publication No. 2021/0305381).
Regarding claim 1, Chiang discloses a semiconductor device fabrication method, comprising: executing front-end-of-line (FEOL) processing to form first and second source/drain (S/D) epitaxy Fig 21B-21E, 260; forming a middle-of-line (MOL) contact to the first S/D epitaxy Fig 21B-21E, 273/275; executing a self-aligned backside S/D cut Fig 20B-20E to form an opening in which respective sides of each of the first and second S/D epitaxy are exposed Fig 20B-20E, 260; depositing metallic material along the respective sides of each of the first and second S/D epitaxy in the opening ¶0048, 0056-0057; and forming silicide Fig 21B-21E, 280 from the metallic material whereby the silicide at the first S/D epitaxy contacts the MOL contact and the sides of the first S/D epitaxy Fig 21B-21E.
Regarding claim 2, Chiang discloses wherein the MOL contact is a gouged contact Fig 14B-14E, 273/275.
Regarding claim 3, Chiang discloses executing a self-aligned backside cut toward the second S/D epitaxy Fig 20B-20E.
Regarding claim 4, Chiang discloses wherein the self-aligned backside cut comprises gouging into the second S/D epitaxy Fig 20B-20E.
Regarding claim 5, Chiang discloses executing backside contact metallization to form a backside contact in contact with the second S/D epitaxy Fig 22A-22B.
Regarding claim 6, Chiang discloses forming a backside power rail (BPR) Fig 22A-22B, 284 ¶0058 in contact with the backside contact; and forming a backside power distribution network (BSPDN) Fig 22A-22B, 286 ¶0058 in contact with the BPR Fig 22A-22B, 284 ¶0058.
Regarding claim 7, Chiang discloses a semiconductor device fabrication method, comprising: executing front-end-of-line (FEOL) processing to form first and second source/drain (S/D) epitaxy Fig 21B-21E, 260; forming a middle-of-line (MOL) contact to the first S/D epitaxy Fig 21B-21E, 273/275;; executing a self-aligned backside S/D cut Fig 20B-20E to form an opening in which respective sides of each of the first and second S/D epitaxy are exposed Fig 20B-20E, 260; selectively etching the respective sides of each of the first and second S/D epitaxy to recess the respective sides of each of the first and second S/D epitaxy Fig 20A and Fig 20D ¶0054; depositing metallic material along the respective sides of each of the first and second S/D epitaxy¶0048, 0056-0057; and forming silicide from the metallic material whereby the silicide Fig 21B-21E, 280 at the first S/D epitaxy contacts the MOL contact and the sides of the first S/D epitaxy Fig 21B-21E.
Regarding claim 8, Chiang discloses wherein the MOL contact is a gouged contact Fig 14B-14E, 273/275.
Regarding claim 9, Chiang discloses executing a self-aligned backside cut toward the second S/D epitaxy Fig 20B-20E.
Regarding claim 10, Chiang discloses wherein the self-aligned backside cut comprises gouging into the second S/D epitaxy Fig 20B-20E.
Regarding claim 11, Chiang discloses executing backside contact metallization to form a backside contact in contact with the second S/D epitaxy Fig 22A-22B and the silicide at the second S/D epitaxy contacts the backside contact and the sides of the second S/D epitaxy Fig 22A-22B.
Regarding claim 12, Chiang discloses forming a backside power rail (BPR) Fig 22A-22B, 284 ¶0058 in contact with the backside contact; and forming a backside power distribution network (BSPDN) Fig 22A-22B, 286 ¶0058 in contact with the BPR Fig 22A-22B, 284 ¶0058.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811