DETAILED ACTION
This correspondence is in response to the communications received 12/08/2025. Claims 4, 12, and 19 have been amended. Claims 4, 9, and 16 have been withdrawn. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of 1-3, 5-8, and 10-15, and 17-20 in the reply filed on December 8, 2025 is acknowledged. Claims 4, 9, and 16 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/08/2025.
In the requirement for restriction, a figure was indicated for each species. The species do not correspond to the entire figure, but rather to the description provided for each species. The figures therefore function as a means to illustrate the corresponding elements and features of each species, but are not themselves entirely representative of the species. Thus, a figure may be used for multiple species, provided each species using the figure appears in a separate election. Furthermore, as each election was regarding a distinct feature of the invention, generic claims indicated in one election may not be generic for other elections.
As requested by the Applicant, the elected species correspond to the embodiment shown in Figs. 1-5.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/30/2023 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
Claims 2, 6, 13, 14, and 18 use the terms concave and/or convex. Merriam-Webster defines concave as “hollowed or rounded inward like the inside of a bowl” and convex as “curved or rounded outward like the exterior of a sphere or circle”. For the purposes of examination, the inward and outward directions will be defined with respect to the element being described. For example, the perimeter of a circle will be defined as completely convex and a “U” shape will be defined as having a concave interior and a concave exterior.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the gate insulating film in each of the inner gate structures" in line 3. There is insufficient antecedent basis for this limitation in the claim. It is unclear whether "the gate insulating film in each of the inner gate structures" is the same element as the “gate insulating film” included in the “the plurality of gate structures”. For the purposes of examination, the limitation will be interpretated as “wherein each include a gate insulating film, and the gate insulating film in each of the inner gate structures is in contact with the source/drain patterns”.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a semiconductor device comprising:
an active pattern (AP) extending in a first direction (D1, see Fig. 1);
a plurality of gate structures (GS) on the active pattern and spaced apart from one another in the first direction (see Fig. 2), each of the plurality of gate structures including a gate electrode (120) extending in a second direction (see Fig. 3) and gate spacers (140) on sidewalls of the gate electrode (see Fig. 2);
source/drain patterns (150) between the plurality of gate structures that are adjacent to one another (see Fig. 2);
source/drain contacts (180) on the source/drain patterns and connected to the source/drain patterns (see Figs. 2 and 4); and
contact silicide films (155) between the source/drain contacts and the source/drain patterns (see Fig. 2),
wherein
outer surfaces of the contact silicide films (155OS) are in contact with the source/drain patterns (see Fig. 2), and inner surfaces of the contact silicide films (155IS) are in contact with the source/drain contacts (see Fig. 2),
uppermost portions of the outer surfaces of the contact silicide films (155OS_UP) are uppermost portions of the contact silicide films (155_UP, see Fig. 2, specifically where 155 is in direct contact with 140),
a width in the first direction of the contact silicide films reaches its maximum (W_MAX) at the uppermost portions of the outer surfaces of the contact silicide films (see Fig. 5),
parts of the outer surfaces of the contact silicide films are in contact with the gate spacers (see Fig. 2), and
the width in the first direction of the contact silicide films at the uppermost portions of the contact silicide films is equal to a width in the first direction of the source/drain contacts (see Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 5, 10, 12, 13, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Bhuwalka et al. (US 20170256609 A1) in view of Hsu et al. (US 10,546,922 B2).
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Regarding claim 1, Figs. 1-4 of Bhuwalka disclose a semiconductor device (see title) comprising:
an active pattern (together “first through third semiconductor patterns 127, 128, and 129”, [0021], and “substrate 100” [0053] form an active pattern, as per [0003] of the instant specification, an active pattern is equivalent to a “silicon body”, thus 100 is a component of the active pattern as “substrate 100 may include a semiconductor material such silicon, germanium or silicon-germanium or a III-V group compound semiconductor”, [0053]) extending in a first direction (as seen in Fig. 3, 127, 128, and 129 extend in the 1st direction);
a plurality of gate structures (“gate structure 250”, [0021]) on the active pattern and spaced apart from one another in the first direction (as seen in Fig. 3, 250 are on 127, 128, and 129 and are spaced apart from one another in the 1st direction), each of the plurality of gate structures including a gate electrode extending in a second direction (as seen in Fig. 3, 250 includes “gate electrode 240”, [0041], as seen in Fig. 4, 240 extends in the 2nd direction) and gate spacers on sidewalls of the gate electrode (as seen in Fig. 3, “inner spacer 180 and the gate spacer 160”, [0041], are on the sidewalls of 240);
source/drain patterns (“fourth semiconductor layer 190 may form a source/drain layer”, [0035]) between the plurality of gate structures that are adjacent to one another (as seen in Fig. 3, 190 is between instances of 250 that are adjacent to one another);
source/drain contacts (“contact plug 320”, [0021], as seen in Fig. 3, 320 is in contact with 190 via “metal silicide pattern 290”, [0021], and is therefore a source/drain contact) on the source/drain patterns and connected to the source/drain patterns (as seen in Fig. 3, 320 is on 190 and connected to 190 via 290); and
contact silicide films (“metal silicide pattern 290”, [0021]”) between the source/drain contacts and the source/drain patterns (as seen in Fig. 3, 290 is between 320 and 190).
Bhuwalka fails to disclose “wherein
outer surfaces of the contact silicide films are in contact with the source/drain patterns, and inner surfaces of the contact silicide films are in contact with the source/drain contacts,
uppermost portions of the outer surfaces of the contact silicide films are uppermost portions of the contact silicide films,
a width in the first direction of the contact silicide films reaches its maximum at the uppermost portions of the outer surfaces of the contact silicide films,
parts of the outer surfaces of the contact silicide films are in contact with the gate spacers, and
the width in the first direction of the contact silicide films at the uppermost portions of the contact silicide films is equal to a width in the first direction of the source/drain contacts.”
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However, in a similar field of endeavor, Fig. 5 of Hsu teaches wherein
outer surfaces of the contact silicide films (“OS” denoted in Fig. 5 are outer surfaces of “silicide 54”, col. 4, line 42, which is equivalent to 290 of Bhuwalka) are in contact with the source/drain patterns (as seen in Fig. 5, OS is in contact with “epitaxial layer 30”, col. 2, line 66, where “epitaxial layer 30 fills most of the recess 26 and may include dopants for forming a source/drain region”, col. 3, lines 1-3, thus 30 is a source/drain pattern, and equivalent to 190 of Bhuwalka), and inner surfaces of the contact silicide films (“IS” denoted in Fig. 5 are inner surfaces of 54) are in contact with the source/drain contacts (as seen in Fig. 5, IS is in contact with “contact plug 48”, col. 4, line 43, where 48 comprises “first metal layer 50”, col. 4, lines 50-51, “second metal layer 52”, col. 4, line 51, and “third metal layer 56”, col. 2, line 66, as 48 is connected to 30, 48 is thus is a source/drain contact , and equivalent to 320 of Bhuwalka),
uppermost portions of the outer surfaces of the contact silicide films are uppermost portions of the contact silicide films (as seen in Fig. 5, the uppermost portions of OS are uppermost portions of 54),
a width in the first direction of the contact silicide films reaches its maximum at the uppermost portions of the outer surfaces of the contact silicide films (as seen in Fig. 5, the width of 54 in the horizontal direction, equivalent to the 1st direction of Bhuwalka, reaches its maximum at the uppermost portions of OS),
parts of the outer surfaces of the contact silicide films are in contact with the gate spacers (after replacing 290 of Bhuwalka with the analogous features of 54 of Hsu, the geometry and location of the element in Bhuwalka will then satisfy this limitation. Examiner believes that this configuration is provided by the combination rejection presented), and
the width in the first direction of the contact silicide films at the uppermost portions of the contact silicide films is equal to a width in the first direction of the source/drain contacts (as seen in Fig. 5, the width of 54 in the horizontal direction at the uppermost portion of 54 is equal to a width in the horizontal direction of 48).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein
outer surfaces of the contact silicide films are in contact with the source/drain patterns, and inner surfaces of the contact silicide films are in contact with the source/drain contacts,
uppermost portions of the outer surfaces of the contact silicide films are uppermost portions of the contact silicide films,
a width in the first direction of the contact silicide films reaches its maximum at the uppermost portions of the outer surfaces of the contact silicide films,
parts of the outer surfaces of the contact silicide films are in contact with the gate spacers, and
the width in the first direction of the contact silicide films at the uppermost portions of the contact silicide films is equal to a width in the first direction of the source/drain contacts” as taught by Hsu in the system of Bhuwalka for the purpose of increasing the surface area between the silicide layer and the neighboring layers.
Regarding claim 2, Figs. 1-4 of Bhuwalka in combination with Fig. 5 of Hsu disclose the semiconductor device of claim 1, Fig. 5 of Hsu further discloses wherein the outer surfaces of the contact silicide films are convex (as seen in Fig. 5, OS is convex where convex is defined by Merriam-Webster as “curved or rounded outward like the exterior of a sphere or circle”), and the inner surfaces of the contact silicide films are concave (as seen in Fig. 5, IS is concave where concave is defined by Merriam-Webster as “hollowed or rounded inward like the inside of a bowl”).
Regarding claim 3, Figs. 1-4 of Bhuwalka in combination with Fig. 5 of Hsu disclose the semiconductor device of claim 2, Fig. 5 of Hsu further discloses wherein the outer surfaces of the contact silicide films are directly connected to the inner surfaces of the contact silicide films (as seen in Fig. 5, OS is directly connected to IS, while OS and IS were labeled in Fig. 5 on separate instances of 54, this was done for readability, each instance of 54 has a corresponding OS and IS).
Regarding claim 5, Figs. 1-4 of Bhuwalka in combination with Fig. 5 of Hsu disclose the semiconductor device of claim 2, Fig. 5 of Hsu further discloses wherein upper surfaces of the contact silicide films (“US” denoted in Fig. 5 are upper surfaces of 54) connect the outer surfaces of the contact silicide films and the inner surfaces of the contact silicide films (as US includes the end portions of IS which are connected to OS, US connects OS and IS)
Together Figs. 1-4 of Bhuwalka and Fig. 5 of Hsu further teach wherein in a cross-sectional view (both Fig. 3 of Bhuwalka and Fig. 5 of Hsu are cross-sectional views), the upper surfaces of the contact silicide films are planes inclined with respect to an upper surface of the active pattern (as seen in Fig. 3 of Bhuwalka, the upper surfaces of 127, 128 and 129 are parallel to the 1st direction, as seen in Fig. 5 of Hsu, US are inclined with respect to the horizontal direction, thus as the 1st direction of Bhuwalka and the horizontal direction of Hsu are equivalent, after substitution of 54 of Hsu for 290 of Bhuwalka, US are inclined with respect to an upper surface of 127, 128, and 129).
Regarding claim 10, Figs. 1-4 of Bhuwalka in combination with Fig. 5 of Hsu disclose the semiconductor device of claim 1, Figs. 1-4 of Bhuwalka further disclose wherein the active pattern includes a lower pattern (100 is a lower pattern) and a plurality of sheet patterns (127, 128, and 129 are a plurality of sheet patterns), the lower pattern extends in the first direction (as seen in Fig. 3, 100 extends in the 1st direction), the plurality of sheet patterns are spaced apart from the lower pattern in a third direction (as seen in Fig. 3, 127, 128, and 129 are spaced apart from 100 in the 3rd direction), each of the plurality of gate structures further includes inner gate structures (as seen in Fig. 3, 250 further includes inner gate structures comprising “gate insulating pattern 230”, [0041], and “gate electrode 240”, [0041]), the inner gate structures are between the lower pattern and the plurality of sheet patterns (as seen in Fig. 3, 230 and 240 are between 100 and 127) and between the plurality of sheet patterns that are adjacent to one another (as seen in Fig. 3, 230 and 240 are between 127 and 128, and 128 and 129).
Regarding claim 12, Figs. 1-4 of Bhuwalka disclose a semiconductor device (see title) comprising:
an active pattern (together “first through third semiconductor patterns 127, 128, and 129”, [0021], and the silicon portion of “substrate 100”, hereinafter “SiP” [0053] form an active pattern, as per [0003] of the instant specification, an active pattern is equivalent to a “silicon body”, thus SiP is a component of the active pattern as “substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate”, [0053]) including a lower pattern (the silicon portion of 100 is a lower pattern) and a plurality of sheet patterns (127, 128, and 129 are a plurality of sheet patterns), the lower pattern extending in a first direction (as seen in Fig. 3, 100 extends in the 1st direction) on a substrate (SiP is on the insulator portion of 100 which functions as a substrate), the plurality of sheet patterns being spaced apart from the lower pattern in a second direction as seen in Fig. 3, 127, 128, and 129 are spaced apart from 100, and therefore SiP, in the 3rd direction), and the plurality of sheet patterns including an uppermost sheet pattern (as seen in Fig. 3, 129 is an uppermost sheet pattern);
a plurality of gate structures (“gate structure 250”, [0021]) on the lower pattern and spaced apart from one another in the first direction (as seen in Fig. 3, 250 are on 100, and therefore SiP, and are spaced apart from one another in the 1st direction), each of the plurality of gate structures including a gate electrode extending in a third direction (as seen in Fig. 3, 250 includes “gate electrode 240”, [0041], as seen in Fig. 4, 240 extends in the 2nd direction) and gate spacers on sidewalls of the gate electrode (as seen in Fig. 3, “inner spacer 180 and the gate spacer 160”, [0041], are on the sidewalls of 240);
source/drain patterns (“fourth semiconductor layer 190 may form a source/drain layer”, [0035]) on the lower pattern (as seen in Fig. 3, 190 are on 100, and therefore SiP) and connected to the plurality of sheet patterns (as seen in Fig. 3, 190 are connected to 127, 128, and 129);
source/drain contacts (“contact plug 320”, [0021], as seen in Fig. 3, 320 is in contact with 190 via “metal silicide pattern 290”, [0021], and is therefore a source/drain contact) on the source/drain patterns and connected to the source/drain patterns (as seen in Fig. 3, 320 is on 190 and connected to 190 via 290); and
contact silicide films (“metal silicide pattern 290”, [0021]”) between the source/drain contacts and the source/drain patterns (as seen in Fig. 3, 290 is between 320 and 190)
wherein
inner sidewalls of the gate spacers face the gate electrode and outer sidewalls of the gate spacers are opposite the inner sidewalls in the first direction (as seen in Fig. 3, inner sidewalls of 160 face 240, and outer sidewalls of 160 are opposite the inner sidewalls in the 1st direction).
Bhuwalka fails to disclose “wherein
outer surfaces of the contact silicide films are in contact with the source/drain patterns, and inner surfaces of the contact silicide films are in contact with the source/drain contacts,
parts of the outer surfaces of the contact silicide films are in contact with the outer sidewalls of the gate spacers,
a width in the first direction of the contact silicide films increases as a distance of the contact silicide films away from the substrate increases, and
a width in the first direction of the contact silicide films at uppermost portions of the contact silicide films is equal to a width in the first direction of the source/drain contacts.”
However, in a similar field of endeavor, Fig. 5 of Hsu teaches wherein
outer surfaces of the contact silicide films (“OS” denoted in Fig. 5 are outer surfaces of “silicide 54”, col. 4, line 42, which is equivalent to 290 of Bhuwalka) are in contact with the source/drain patterns (as seen in Fig. 5, OS is in contact with “epitaxial layer 30”, col. 2, line 66, where “epitaxial layer 30 fills most of the recess 26 and may include dopants for forming a source/drain region”, col. 3, lines 1-3, thus 30 is a source/drain pattern, and equivalent to 190 of Bhuwalka), and inner surfaces of the contact silicide films (“IS” denoted in Fig. 5 are inner surfaces of 54) are in contact with the source/drain contacts (as seen in Fig. 5, IS is in contact with “contact plug 48”, col. 4, line 43, where 48 comprises “first metal layer 50”, col. 4, lines 50-51, “second metal layer 52”, col. 4, line 51, and “third metal layer 56”, col. 2, line 66, as 48 is connected to 30, 48 is thus is a source/drain contact , and equivalent to 320 of Bhuwalka),
parts of the outer surfaces of the contact silicide films are in contact with the outer sidewalls of the gate spacers (after replacing 290 of Bhuwalka with the analogous features of 54 of Hsu, the geometry and location of the element in Bhuwalka will then satisfy this limitation. Examiner believes that this configuration is provided by the combination rejection presented),
a width in the first direction of the contact silicide films increases as a distance of the contact silicide films away from the substrate increases (after substitution of 54 of Hsu for 290 of Bhuwalka a width in the 1st direction of 54 of Hsu increases as a distance of 54 of Hsu away from the insulator portion of 100 of Bhuwalka increases), and
a width in the first direction of the contact silicide films at uppermost portions of the contact silicide films is equal to a width in the first direction of the source/drain contacts (as seen in Fig. 5, the width of 54 in the horizontal direction at the uppermost portion of 54 is equal to a width in the horizontal direction of 48).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein
outer surfaces of the contact silicide films are in contact with the source/drain patterns, and inner surfaces of the contact silicide films are in contact with the source/drain contacts,
parts of the outer surfaces of the contact silicide films are in contact with the outer sidewalls of the gate spacers,
a width in the first direction of the contact silicide films increases as a distance of the contact silicide films away from the substrate increases, and
a width in the first direction of the contact silicide films at uppermost portions of the contact silicide films is equal to a width in the first direction of the source/drain contacts” as taught by Hsu in the system of Bhuwalka for the purpose of increasing the surface area between the silicide layer and the neighboring layers.
Regarding claim 13, Figs. 1-4 of Bhuwalka in combination with Fig. 5 of Hsu disclose the semiconductor device of claim 12, Fig. 5 of Hsu further discloses wherein the outer surfaces of the contact silicide films are convex (as seen in Fig. 5, OS is convex where convex is defined by Merriam-Webster as “curved or rounded outward like the exterior of a sphere or circle”), and the inner surfaces of the contact silicide films are concave (as seen in Fig. 5, IS is concave where concave is defined by Merriam-Webster as “hollowed or rounded inward like the inside of a bowl”).
Regarding claim 17, Figs. 1-4 of Bhuwalka in combination with Fig. 5 of Hsu disclose the semiconductor device of claim 12, Figs. 1-4 of Bhuwalka further disclose wherein each of the plurality of gate structures further includes inner gate structures (as seen in Fig. 3, 250 further includes inner gate structures comprising “gate insulating pattern 230”, [0041], and “gate electrode 240”, [0041]), the inner gate structures are between the lower pattern and the plurality of sheet patterns (as seen in Fig. 3, 230 and 240 are between 100, and therefore SiP, and 127) and between the plurality of sheet patterns that are adjacent to one another (as seen in Fig. 3, 230 and 240 are between 127 and 128, and 128 and 129), the inner gate structures include a first inner gate structure (the instance of 240 and 230 between 128 and 129 as seen in Fig. 3 is a first inner gate structure, hereinafter “FG”) and a second inner gate structure (the instance of 240 and 230 between 127 and 128 as seen in Fig. 3 is a second inner gate structure, hereinafter “SG”), the second inner gate structure is between the lower pattern and the first inner gate structure (as seen in Fig. 3, SG is between 100, and therefore SiP, and FG), and a width in the first direction of the first inner gate structure is equal to a width in the first direction, of the second inner gate structure (as seen in Fig. 3, a width in the 1st direction of FG is equal to a width in the 1st direction, of SG).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Bhuwalka et al. (US 20170256609 A1) in view of Hsu et al. (US 10,546,922 B2) in view of Su et al. (US 20220271138 A1).
Regarding claim 8, Figs. 1-4 of Bhuwalka in combination with Fig. 5 of Hsu disclose the semiconductor device of claim 1.
Bhuwalka in combination with Hsu fails to disclose “wherein the source/drain contacts have a single-conductive-layer structure”.
However, in a similar field of endeavor, Figs. 1-16 of Su teach wherein the source/drain contacts have a single-conductive-layer structure (“backside source/drain contact 274 may optionally include a barrier layer 273”, [0026], further Su states “a metal fill material may be deposited into the first backside source/drain contact opening 272 to form the backside source/drain contact 274, as shown in FIG. 7. The metal fill material may include tungsten (W), ruthenium (Ru), cobalt (Co), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)”, [0026], where 274 of Su is equivalent to 320 of Bhuwalka, thus 320 of Bhuwalka may comprise solely of “metal pattern 310”, [0047] without “barrier pattern 300”, [0047]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the source/drain contacts have a single-conductive-layer structure” as taught by Su in the system of Bhuwalka in combination with Hsu for the purpose of reducing device complexity and streamline manufacturing.
Allowable Subject Matter
Claims 6, 7, 14, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the semiconductor device as recited in the claims of the instant application.
Regarding claim 6, the prior art of Bhuwalka et al. (US 20170256609 A1) in combination with Hsu et al. (US 10,546,922 B2) discloses a semiconductor device but fails to disclose the specific claims of the instant application regarding the geometry of the contact silicide film e.g. “wherein the inner surfaces of the contact silicide films include first convex regions and second convex regions, which are connected to each other”.
Regarding claim 7, the prior art of Bhuwalka et al. (US 20170256609 A1) in combination with Hsu et al. (US 10,546,922 B2) discloses a semiconductor device but fails to disclose the specific claims of the instant application regarding a seam pattern in the contact silicide film e.g. “wherein the contact silicide films further include seam patterns”. As Bhuwalka and Hsu both disclose thermal processes to form their respective contact silicide films at the interface of neighboring layers, a seam pattern would be incompatible as an annealing process would not generate a seam in the existing layers.
Regarding claim 14, the prior art of Bhuwalka et al. (US 20170256609 A1) in combination with Hsu et al. (US 10,546,922 B2) discloses a semiconductor device but fails to disclose the specific claims of the instant application regarding the geometry of the contact silicide film e.g. “wherein the inner surfaces of the contact silicide films include first convex regions and second convex regions”.
Regarding claim 15, the prior art of Bhuwalka et al. (US 20170256609 A1) in combination with Hsu et al. (US 10,546,922 B2) discloses a semiconductor device but fails to disclose the specific claims of the instant application regarding a seam pattern in the contact silicide film e.g. “wherein the contact silicide films further include seam patterns”. As Bhuwalka and Hsu both disclose thermal processes to form their respective contact silicide films at the interface of neighboring layers, a seam pattern would be incompatible as an annealing process would not generate a seam in the existing layers.
Claim 11 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 11, the prior art of Bhuwalka et al. (US 20170256609 A1) in combination with Hsu et al. (US 10,546,922 B2) discloses a semiconductor device but fails to disclose the specific claims of the instant application regarding the structure of the gate insulating films and the source/drain patterns e.g. “the gate insulating film in each of the inner gate structures is in contact with the source/drain patterns”.
Claims 18-20 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the semiconductor device as recited in the claims of the instant application.
Regarding claim 18, the prior art of Bhuwalka et al. (US 20170256609 A1) in combination with Hsu et al. (US 10,546,922 B2) discloses a semiconductor device but fails to disclose the specific claims of the instant application regarding the geometry of the inner and outer surfaces of the contact silicide film, e.g. “uppermost portions of the outer surfaces of the contact silicide films are higher than uppermost portions of the inner surfaces of the contact silicide films”.
Claims 19-20 are allowable by virtue of their dependence on claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893