DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/05/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 2 is objected to because of the following informalities:
It is noted that there are two claim 2 as being dependent of claim 1. Claim “2.” before claim 4, should correctly ---3.---.
. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 11 & 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ortiz et al. (US 20190296703 A1) in view of Ten Dolle et al. (US 20050140440 A1), hereinafter, Ortiz and Ten Dolle.
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Fig. 2 of Ortiz et al.
Regarding claim 11, Ortiz (Fig. 2) discloses an apparatus comprising:
an amplifier (20) being connected between an input terminal (50) and a first primary terminal (14) and an amplifier (26) being connected between an input terminal 52 and second primary terminal (18) and wherein the amplifiers 20 & 26 form a differential amplifier.
Ortiz does not disclose a first pair of transistors configured to receive a first voltage input and a second voltage input respectively at their gate terminals;
a second pair of transistors comprising respective sources coupled to respective drains of the first pair of transistors, the second pair of transistors being configured to provide a differential voltage signal based on the first voltage input and the second voltage input.
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Fig. 1 of Ten Dolle et al.
Ten Dolle (Fig. 1) discloses amplifier circuit comprising:
a first pair of transistors (transistors 100 & 110, it is noted that paragraph [0026] which states “the bipolar transistors 100, 104, 104, 114 may be replaced by field effect transistors”, noted that the 104 on right having typo and it should correctly be “110”, thus all transistors as shown in Fig. 1 may be read as FET transistors) configured to receive a first voltage input and a second voltage input respectively at their gate terminals;
a second pair of transistors (transistor 104 & 114) comprising respective sources coupled to respective drains of the first pair of transistors (transistors 100 & 110), the second pair of transistors (transistors 104 & 114) being configured to provide a differential voltage signal based on the first voltage input and the second voltage input.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the generic differential amplifier of Ortiz to have specific differential amplifier as taught by Ten Dolle. Such a modification would have imparted the advantageous benefit of gain and linearity, see paragraphs [0005] and [0030]), as taught by, to Ten Dolle reference, thereby suggesting the obviousness of such a modification.
As a consequence of the combination, the combination further discloses a transformer (transformer T1) comprising a primary winding (12) and a secondary winding (36), the primary winding being coupled to respective drains of the second pair of transistors (transistors pair 104 & 114) to receive a current signal associated with the differential voltage signal, the primary winding (12 of Fig. 2, Ortiz ) comprising a midpoint (center-tap terminal 16) that separates the primary winding to two sections with equal resistances, the secondary (36, Fig. 2 of Ortiz) being coupled between a ground terminal and an output terminal (terminal 40, Fig. 2 of Ortiz); and
at least a programmable capacitor (variable or tunable capacitor 80, Fig. 2 of Ortiz) coupled between the midpoint of the primary winding (12) and a first common node (see node 126, Fig. 1 of Ten Dolle) that is coupled to the first pair of transistors (transistors 100 & 110).
Regarding claim 15, the combination discloses the apparatus of claim 11, wherein the programmable capacitor comprises a switched capacitor array (see paragraph [0008] of Ortiz, programmable capacitor array).
Regarding claim 16, the combination discloses the apparatus of claim 11, wherein the programmable capacitor (variable capacitor 80 of Fig. 2 of Ortiz) comprises a MEMS-based capacitor (commonly well-known in the art where programmable tunable or variable capacitor can be configured as MEMS-based capacitor, see reference US 2008/0303597 A1 to INOUE, Claim 10 which states “the variable capacitor element is a MEMS (Micro Electro Mechanical Systems) element”).
Allowable Subject Matter
Claims 12-14 & 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-10 & 19-20 are allowed.
Upon conclusion of a comprehensive search of the pertinent prior art, the Office indicates that the claims are allowable.
The prior art when taken alone, or, in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged, disposed, or provided in the manner as claimed by the Applicant. Added primarily for emphasis, the claim recitations “the second winding comprising a third terminal being grounded via a sixth resistor and a fourth terminal serving as an output terminal; and a third circuit comprising a first resistor, a second common node, a second resistor, a programmable capacitor, a third resistor, a first common node, and a fourth resistor coupled in series sequentially from a midpoint of the first winding to a ground terminal” in Claim 1, and “coupling a power supply to a second common node of the center-tap line that is connected to the midpoint of the first winding via a first resistor and connected to the programmable capacitor via a second resistor; and coupling the first common node to the programmable capacitor via a third transistor and to ground via a fourth resistor” in Claim 19 are not found in the prior art of record.
Claims 2-10 are allowable as being dependent of claim 1. Claim 20 is allowable as being dependent of claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843