DETAILED ACTION
This correspondence is in response to the communications received 04/08/2026. Claims 21-23 have been added. Claim 20 has been amended. Claims 1-9 have been canceled. Claims 10-23 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment to the title overcomes the objection outlined in the previous Office Action. The objection is withdrawn.
Applicant’s amendment to claim 20 overcomes the objection outlined in the previous Office Action. The objection is withdrawn.
Response to Arguments
Applicant's arguments filed 04/08/2026 on pages 7-11 of the Remarks have been fully considered but they are not persuasive.
With regards to section A, Applicant asserts that Ryu et al. (US 20220013524 A1) fails to disclose all the features of claim 1. Specifically, that Ryu fails to disclose or otherwise suggest the “composite material layer comprising a bit line in the connection region”.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., "the initial material layers 22 in the initial stack structure have been converted into composite material layers 23" and "The composite material layer 23 includes the bit line 81 in the connection region B" from [0068]-[0069] of the instant specification, and the orientation of the bit line structure) are not recited in the rejected claim. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). As Ryu in combination with Choi et al. (US 20230138478 A1) and Ahn et al. (US 20220157822 A1) disclose all of the limitations of claim 10, the argument is moot.
Applicant also argues that equating Ryu’s “first source/drain region SD1” with Applicant’s bit line is improper as SD1 is a region within “active layer ACT”. However as discussed in the previous Office Action, “bit line BL” of Ryu connects “to a first edge portion of the active layer ACT”, [0037], and Choi teaches that the polysilicon or undoped polysilicon of ACT of Ryu can be a bit line, thus SD1 which connects to BL can be considered an extension of BL as it acts to connect BL to the device. Therefore, Ryu in combination with Choi and Ahn disclose a “composite material layer comprising a bit line in the connection region”.
With regards to section B, Applicant argues that the combination of references presented in the previous Office Action would fundamentally alter the operation of Ryu. Specifically, that the including horizontally oriented bit lines formed within composite material layers in a connection region would require a complete redesign of the structure disclosed by Ryu. However, as presented in the previous Office action, the horizontally oriented bit lines, SD1, and the composite material layers, “capping layer CPL” and ACT are already present in the structure taught by Ryu. Thus, there is no fundamental change to the structure of Ryu after combination with the secondary references, and no alteration to the operation of the device of Ryu, merely a reclassification of existing layers.
With regards to section C, Applicant argues that the claimed “connection region” is not taught by any of the references. Specifically, that the claimed “connection region” is “not merely a non-descript phrase, but is rather a meaningful functional descriptor that connotes specific meaning based on the teachings of Applicant’s specification.
However, In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the specific meaning of connection region recited in the specification) are not recited in the rejected claim. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Thus, the “connection region” is interpretated as a portion of the overall device in which electrical connections are made, as discussed in the previous Office Action, “CR” is such a region.
With regards to section D, Applicant argues that the teaching of Choi is not applicable to Ryu. Specifically, that Choi generally teaches an interlayer insulating layer, and does not provide guidance on how to modify Ryu. However, as discussed in the previous Office Action, Ryu discloses “the horizontal support LSPT may include an insulation material, such as silicon oxide”, [0040], further, Choi teaches that an interlayer insulating layer “may be formed of at least one of a silicon oxide and a silicon nitride”, [0097]. There is, therefore, no actual modification of the physical structure of Ryu, instead Choi is utilized to teach that an already existing layer in Ryu serves the same functionality as the claimed interlayer insulating layer. One having ordinary skill in the art would recognize that regardless of context, interlayer insulating layers can be used to electrically isolate layers in a semiconductor device, whether it is a bonding structure between circuit regions or a memory cell.
With regards to section E, Applicant argues that Ahn does not teach a “composite material layer comprising a bit line”. However, as discussed in the previous Office Action, Ahn is only relied upon to teach that SD1 and ACT of Ryu, in combination with CPL also of Ryu, form a composite material layer that comprises a bit line. Thus, Ryu in combination with Ahn discloses “composite material layer comprising a bit line”.
With regards to section F, Applicant argues that there was not motivation to combine the teachings of Ahn, Ryu and Choi. Specifically, that Ryu is already a functional device, and there would be no reason to modify it, that the references teach away from the combination made, and that the cited purpose to combine does not address the problem solved by the Applicant’s disclosure.
Regarding the existing functionality of Ryu, the mere fact that Ryu’s device is functional does not disqualify any potential modifications. Further, the modification presented in the previous Office Action in the rejection of claim 10 does not inherently change the structure of Ryu, and therefore does not change its functionality, the reference polysilicon is already existent in the structure of Ryu, Ahn is merely used to teach the functionality of SD1 of Ryu as an extension of the bit line of Ryu, thus there is no change to the connection structure.
Regarding the alleged teaching away of the references from the combination, as discussed in the previous Office Action and above, the combination of prior art in the rejection of claim 10 does not change the structure of Ryu, instead the secondary references are used to teach that the already existing elements of Ryu map onto the claimed elements. As discussed in the previous Office Action, the combination is specifically compatible due to the shared material compositions of the elements taught by Ryu and the secondary reference. Thus, it is impossible for the secondary references to teach away from the primary reference as they do not modify the structure only demonstrate how it maps to the claimed invention.
Regarding the cited purpose not matching the problem solved in the disclosure, motivation to combine the teachings of the prior art need not be limited to the exact problem presented by the Applicant, and can instead be found from many areas that were known at the time of invention. See MPEP 2143.01.
MPEP 2143.01: Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. In re Kahn, 441 F.3d 977, 986, 78 USPQ2d 1329, 1335 (Fed. Cir. 2006) … "motivation to combine may be found explicitly or implicitly in market forces; design incentives; the ‘interrelated teachings of multiple patents’; ‘any need or problem known in the field of endeavor at the time of invention and addressed by the patent’; and the background knowledge, creativity, and common sense of the person of ordinary skill." Zup v. Nash Mfg., 896 F.3d 1365, 1371, 127 USPQ2d 1423, 1427 (Fed. Cir. 2018) (quoting Plantronics, Inc. v. Aliph, Inc., 724 F.3d 1343, 1354 [107 USPQ2d 1706] (Fed. Cir. 2013) (citing Perfect Web Techs., Inc. v. InfoUSA, Inc., 587 F.3d 1324, 1328 [92 USPQ2d 1849] (Fed. Cir. 2009) (quoting KSR, 550 U.S. at 418-21)).
With regards to section G, Applicant argues that claims 11 and 12 include additional limitations not addressed in the previous Office Action. Specifically, that the “isolation layer” layer required in claim 11 is distinct from the barrier layer taught by Choi. However, as discussed in the previous Office Action, the barrier layer taught by Choi meets all the limitations imposed on the claimed “isolation layer”. The claims do not require or specify what the “isolation layer” is isolating, merely that it is “disposed around the conductive layer”. From Choi: “Each of the contact plugs 252, 253, and 254 may include a conductive layer and a barrier layer surrounding side surfaces and one end of the conductive layer”, [0058], thus the barrier layer is disposed around the conductive layer, and as per Merriam-Webster, a barrier is defined as “something material that blocks or is intended to block passage”, therefore the barrier layer of Choi is an isolation layer as it blocks the diffusion of and thus isolates the atoms of the BL of Ryu. Thus, all of the limitations of claims 11 and 12 are addressed, and the rejection is maintained.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 requires “wherein the bit line is adjacent on three sides to insulating layers”, however claim 10 requires “a stack structure comprising a device region and a connection region arranged in a first direction, the stack structure comprising an interlayer insulating layer and a composite material layer alternatively stacked in a second direction, the composite material layer comprising a bit line in the connection region”. The only insulating layers required by either claim 10 or claim 21 are the “interlayer insulating layers” which are alternatingly stacked with the composite layer. It is unclear, therefore how the composite material layer and bit line is surrounded on three sides by the interlayer insulating layer as required by claim 21. The alternating structure of claim 10 would imply that the bit line is adjacent only on two sides, the top and bottom. Claim 21 is thus indefinite.
Claim 23 requires “wherein the bit line extends outward in the second direction between interlayer insulating layers from an insulating layer vertically spanning the stack structure on one side.” Claim 10 requires “a stack structure comprising a device region and a connection region arranged in a first direction, the stack structure comprising an interlayer insulating layer and a composite material layer alternatively stacked in a second direction, the composite material layer comprising a bit line in the connection region”. Based on the limitations of claim 10, the bit line exists solely in the composite material layer between interlayer insulating layers, therefore it is unclear how it can extend outward in the second direction, which is the direction in which the various layers are stacked. Further, the terms “outward” and “vertically” are unclear as to their relationship to the first and second directions introduced in claim 10. Claim 23 is thus indefinite.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 10, a semiconductor device, comprising:
a stack structure (2) comprising a device region (A) and a connection region (B) arranged in a first direction (X), the stack structure comprising an interlayer insulating layer (21) and a composite material layer (23) alternatively stacked in a second direction (Y), the composite material layer comprising a bit line (81) in the connection region (see Fig. 5), and the second direction intersecting the first direction (see Fig. 5); and
a contact structure (8) in the connection region (see Fig. 5), the contact structure extending to the bit line from a first side of the stack structure in the second direction and connected with the bit line (see Fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 20220013524 A1, hereinafter "Ryu") in view of Choi et al. (US 20230138478 A1, hereinafter Choi) in view of Ahn et al. (US 20220157822 A1, hereinafter “Ahn”).
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Regarding claim 10, Figs. 1A-1D of Ryu disclose a semiconductor device (“semiconductor device 100”), comprising:
a stack structure (as seen in Fig. 1C, 100 has a stack structure comprising “horizontal support LSPT”, “capping layer CPL”, and “active layers ACT”) comprising a device region (the region denoted as “DR” in Fig. 1C is a device region) and a connection region (the region denoted as “CR” in Fig. 1C is a connection region) arranged in a first direction (as seen in Fig. 1C, DR and CR are arranged in the “second direction D2”), the stack structure comprising an interlayer insulating layer (“horizontal support LSPT”, “the horizontal support LSPT may include an insulation material, such as silicon oxide”, [0040], Ryu does not specify that LSPT is an interlayer insulating layer, therefore a secondary reference will be used to teach this limitation below) and a composite material layer (together CPL and ACT form a material layer hereinafter “CML”, as “capping layer CPL may include a low-k material”, [0050], and “active layer ACT may include polysilicon, undoped polysilicon, amorphous silicon, or an oxide semiconductor material”, [0037], the CML is thus a composite material layer as it is formed of a variety of different materials) alternatively stacked in a second direction (as seen in Fig. 1C, LSPT and the layers of CML are alternatively stacked in “first direction D1”), the composite material layer comprising a bit line (“first source/drain region SD1”, Ryu does not specify that SD1 is a bit line, therefore a secondary reference will be used to teach this limitation below) in the connection region (as seen in Fig. 1C, SD1 is in CR), and the second direction intersecting the first direction (as seen in Fig. 1C, D1 is intersecting D2); and
a contact structure (as “the bit line BL may include a conductive material”, [0030], and “the bit line BL may be electrically connected to a first edge portion of the active layer ACT”, [0037], therefore BL in combination with CPL is a contact structure) in the connection region (as seen in Fig. 1C, BL is in CR), the contact structure extending to the bit line from a first side of the stack structure in the second direction (as seen in Fig. 1C, BL extends to SDL from the topside of the stack structure in D1) and connected with the bit line (as seen in Fig. 1C, BL is connected with SD1).
Figs. 1A-1D of Ryu fail to specify “an interlayer insulating layer, the composite material layer comprising a bit line”.
However, in a similar field of endeavor, Fig. 2 of Choi teaches an interlayer insulating layer (“the interlayer insulating layer 220 may be formed of at least one of a silicon oxide and a silicon nitride”, [0097], therefore LSPT of Ryu which is also formed of silicon oxide is also an interlayer insulating layer as it is also formed between other material layers).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “an interlayer insulating layer” as taught by Choi in the system of Ryu for the purpose of preventing electrical crosstalk between various device layers.
The combination of Figs. 1A-1D of Ryu and Fig. 2 of Choi fail to disclose “the composite material layer comprising a bit line”.
However, in a similar field of endeavor, Figs. 1A-1B of Ahn teach the composite material layer comprising a bit line (“first bit-line pattern 150 may include or may be formed of impurity-doped polysilicon or impurity-undoped polysilicon”, [0021], thus SD1 and ACT of Ryu, which as previously discussed are formed of polysilicon or undoped polysilicon, are a bit-line)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the composite material layer comprising a bit line” as taught by Ahn in the system of Ryu in combination with Choi for the purpose of using polysilicon to electrically connect to specific semiconductor channels.
Regarding claim 11, Figs. 1A-1D of Ryu in combination with Fig. 2 of Choi and Figs. 1A-1B of Ahn disclose the semiconductor device of claim 10, Figs. 1A-1D of Ryu further disclose wherein the contact structure comprises a conductive layer (as previously discussed, BL is a conductive layer) and an isolation layer disposed around the conductive layer (Ryu does not disclose an isolation layer, however a secondary reference will be used to disclose this limitation below), wherein the conductive layer is connected with the bit line (as discussed previously, BL is electrically connected with SD1).
Fig. 2 of Choi further discloses an isolation layer disposed around the conductive layer (“Each of the contact plugs 252, 253, and 254 may include a conductive layer and a barrier layer surrounding side surfaces and one end of the conductive layer”, [0058], where the conductive layer of Choi is equivalent to BL of Ryu, and as per Merriam-Webster, a barrier is defined as “something material that blocks or is intended to block passage”, therefore the barrier layer of Choi is an isolation layer as it blocks the diffusion of and thus isolates the atoms of the BL of Ryu)
Regarding claim 12, Figs. 1A-1D of Ryu in combination with Fig. 2 of Choi and Figs. 1A-1B of Ahn disclose the semiconductor device of claim 11, Figs. 1A-1D of Ryu further disclose wherein the conductive layer extends to the bit line from the first side of the stack structure in the second direction (as seen in Fig. 1C, BL extends to SDL from the topside of the stack structure in D1).
Fig. 2 of Choi further discloses the isolation layer covers side walls of the conductive layer (as discussed previously, the barrier layer surrounds the side surfaces of the conductive layer, where the side surfaces are equivalent to the side walls).
Regarding claim 14, Figs. 1A-1D of Ryu in combination with Fig. 2 of Choi and Figs. 1A-1B of Ahn disclose the semiconductor device of claim 10, Figs. 1A-1D of Ryu further disclose further comprising a gate structure (together “word line WL” and “gate dielectric layer GD” form a gate structure, while Ryu does not specify that WL is a gate, Ryu does state that “transistor TR may include an active layer ACT, a gate dielectric layer GD, and a word line WL”, [0032], and that “the word line WL may include a metal, a metal mixture, a metal alloy, or a semiconductor material”, [0035], therefore as a metal layer separated from an active layer by a gate dielectric, it would be obvious to one skilled in the art that WL is a gate and therefore part of the gate structure) in the device region (as seen in Fig. 1C, WL and GD are in DR), wherein the gate structure penetrates through the stack structure in the second direction (as seen in Fig. 1C, GD and WL penetrate through LSPT, CPL, and ACT in D1); and
wherein the gate structure comprises a gate (WL) and a gate insulating layer (GD), wherein the gate penetrates through the stack structure in the second direction (as seen in Fig. 1C, WL penetrates through LSPT and CPL in D1), and the gate insulating layer is located between the gate and the stack structure (as seen in Fig. 1C, GD is between WL and ACT).
Regarding claim 20, Figs. 1A-1D of Ryu disclose a memory system (together “memory cell array MCA” and “base substrate LS” including “peripheral circuit unit PC” form a memory system), comprising:
a memory (“memory cell array MCA”) comprising a semiconductor device (“semiconductor device 100”), the semiconductor device comprising:
a stack structure (as seen in Fig. 1C, 100 has a stack structure comprising “horizontal support LSPT”, “capping layer CPL”, and “active layers ACT”) comprising a device region (the region denoted as “DR” in Fig. 1C is a device region) and a connection region (the region denoted as “CR” in Fig. 1C is a connection region) arranged in a first direction (as seen in Fig. 1C, DR and CR are arranged in the “second direction D2”), the stack structure comprising an interlayer insulating layer (“horizontal support LSPT”, “the horizontal support LSPT may include an insulation material, such as silicon oxide”, [0040], Ryu does not specify that LSPT is an interlayer insulating layer, therefore a secondary reference will be used to teach this limitation below) and a composite material layer (together CPL and ACT form a material layer hereinafter “CML”, as “capping layer CPL may include a low-k material”, [0050], and “active layer ACT may include polysilicon, undoped polysilicon, amorphous silicon, or an oxide semiconductor material”, [0037], the CML is thus a composite material layer as it is formed of a variety of different materials) alternatively stacked in a second direction (as seen in Fig. 1C, LSPT and the layers of CML are alternatively stacked in “first direction D1”), (“first source/drain region SD1”, Ryu does not specify that SD1 is a bit line, therefore a secondary reference will be used to teach this limitation below) in the connection region (as seen in Fig. 1C, SD1 is in CR), and the second direction intersecting the first direction (as seen in Fig. 1C, D1 is intersecting D2);
a contact structure (as “the bit line BL may include a conductive material”, [0030], and “the bit line BL may be electrically connected to a first edge portion of the active layer ACT”, [0037], therefore BL in combination with CPL is a contact structure) in the connection region (as seen in Fig. 1C, BL is in CR), the contact structure extending to the bit line from a first side of the stack structure in the second direction (as seen in Fig. 1C, BL extends to SDL from the topside of the stack structure in D1) and connected with the bit line (as seen in Fig. 1C, BL is connected with SD1).
a controller electrically connected with the memory (“the base substrate LS may include a peripheral circuit unit PC. The peripheral circuit unit PC may include a plurality of control circuits for controlling the memory cell array MCA”, [0027], further, “at least one control circuit of the peripheral circuit unit PC may be electrically connected to the bit line BL”, [0028]).
Figs. 1A-1D of Ryu fail to specify “an interlayer insulating layer, the composite material layer comprising a bit line”.
However, in a similar field of endeavor, Fig. 2 of Choi teaches an interlayer insulating layer (“the interlayer insulating layer 220 may be formed of at least one of a silicon oxide and a silicon nitride”, [0097], therefore LSPT of Ryu which is also formed of silicon oxide is also an interlayer insulating layer as it is also formed between other material layers)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “an interlayer insulating layer” as taught by Choi in the system of Ryu for the purpose of preventing electrical crosstalk between various device layers.
The combination of Figs. 1A-1D of Ryu and Fig. 2 of Choi fail to disclose “the composite material layer comprising a bit line”.
However, in a similar field of endeavor, Figs. 1A-1B of Ahn teach the composite material layer comprising a bit line (“first bit-line pattern 150 may include or may be formed of impurity-doped polysilicon or impurity-undoped polysilicon”, [0021], thus SD1 and ACT of Ryu, which as previously discussed are formed of polysilicon or undoped polysilicon, are a bit-line).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the composite material layer comprising a bit line” as taught by Ahn in the system of Ryu in combination with Choi for the purpose of using polysilicon to electrically connect to specific semiconductor channels.
Regarding claim 21, Figs. 1A-1D of Ryu in combination with Fig. 2 of Choi and Figs. 1A-1B of Ahn disclose the semiconductor device of claim 10, Figs. 1A-1D of Ryu further disclose wherein the bit line is adjacent on three sides to insulating layers (as seen in Figs. 1C, SD1 is adjacent to LSPT on the top and bottom sides, as previously discussed, LSPT is an insulating layer, further as seen in Fig. 1B, SD1 is adjacent to “vertical support VSPT”, where “The vertical support VSPT and the horizontal support LSPT may include the same material. The vertical support VSPT and the horizontal support LSPT may include an insulation material, such as silicon oxide”, col. 6, lines 19-22), two of which being separate respective interlayer insulating layers of the stack structure (as seen in Fig. 1C, two of the adjacent insulating layers are separate respective instances of LSPT).
Regarding claim 22, Figs. 1A-1D of Ryu in combination with Fig. 2 of Choi and Figs. 1A-1B of Ahn disclose the semiconductor device of claim 10, Figs. 1A-1D of Ryu further disclose wherein the composite material layer further comprises a source and a drain in the device region (as seen in Fig. 1, the portion of SD1 in the DR is a source/drain, where the portion of SD2 in CR is part of the bit line, and “source/drain region SD2” is the complimentary source/drain, which is also in DR).
Allowable Subject Matter
Claims 13 and 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the semiconductor device as recited in the claims of the instant application.
Regarding claim 13, the prior art of Ryu et al (US 20220013524 A1) in combination with Choi et al. (US 20230138478 A1) and Ahn et al. (US 20220157822 A1) discloses a semiconductor device but fails to disclose the specific claims of the instant application e.g. the structure of the bit lines and the contact structures, specifically “a plurality of the contact structures disposed in one-to-one correspondence with a plurality of the bit lines”. While Choi does teach a plurality of contact structures directly paired with a corresponding active layer of a plurality of active layers, the structure of Ryu uses a combination of shared word lines and shared bit lines to address individual memory sites, thus these specific aspects of the structures of Ryu and Choi are incompatible.
Regarding claim 15, the prior art of Ryu et al (US 20220013524 A1) in combination with Choi et al. (US 20230138478 A1) and Ahn et al. (US 20220157822 A1) discloses a semiconductor device but fails to disclose the specific claims of the instant application e.g. the arrangement of the plate line relative to the stack structure, specifically “wherein the plate line penetrates through the stack structure in the second direction”.
Claims 16-19 are allowable by virtue of their dependence on claim 15.
Claim 23 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the semiconductor device as recited in the claims of the instant application.
Regarding claim 23, the prior art of Ryu et al (US 20220013524 A1) in combination with Choi et al. (US 20230138478 A1) and Ahn et al. (US 20220157822 A1) discloses a semiconductor device but fails to disclose the specific claims of the instant application e.g. the arrangement of the bit line relative to the insulating layers and the stack structure, specifically “wherein the bit line extends outward in the second direction between interlayer insulating layers from an insulating layer vertically spanning the stack structure on one side”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights