Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18458589 filed on 08/30/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election with traverse of claims 1-11 in the reply filed on 01/07/2026 is acknowledged.
Applicant argues that there is no serious search burden between the device and method claims because the search of Group I would encompass the search of Group II.
The traversal is unpersuasive since the device can be formed by different processes as noted in the restriction requirement and would therefore require separate distinct search strategies for the device and method claims. Additionally, as noted in the restriction requirement Group I and Group II require different CPC group/subgroup searches. Therefore, there would be a serious search and/or examination burden.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Bowman et al. (US 2015/0123240).
Regarding Independent claim 1, Bowman et al. teach a vertical semiconductor device, comprising:
a semiconductor body comprising a substrate (Fig. 7b, element 102, paragraph 0061) and an epitaxial layer (Fig. 7b, elements 104 & 106, paragraph 0063) arranged on the substrate,
wherein the epitaxial layer comprises a first semiconductor region of a first conductivity type (Fig. 7b, element 104, paragraph 0063 discloses n type), and a second semiconductor region (Fig. 7b, element 106, paragraph 0063) of a second conductivity type different from the first conductivity type,
wherein the second semiconductor region is arranged opposite to the substrate with respect to the first semiconductor region (Fig. 7b), and
wherein the first semiconductor region and the second semiconductor region each extend across an entire area of the semiconductor body when viewed in a first direction from the epitaxial layer to the substrate (Fig. 7b);
a trench (Fig. 7b, element 110, paragraph 0064) arranged in the semiconductor body, wherein the trench extends through the second semiconductor region and at least partially into the first semiconductor region, thereby dividing the second semiconductor region into an inner portion and an outer portion that are mutually electrically isolated (Fig. 7b, the trench is filled with dielectric, paragraph 0066);
a first conductive contact (Fig. 7b, element 116, paragraph 0069) arranged on the second semiconductor region and being configured to enable electrically accessing the inner portion; and
a second conductive contact (Fig. 7b, element 118, paragraph 0069) configured to enable electrically accessing the first semiconductor region, wherein the second conductive contact is arranged on the substrate opposite the first semiconductor region,
wherein the substrate is of the first conductivity type (paragraph 0061 discloses n type), and wherein the second conductive contact is electrically connected to the first semiconductor region through the substrate (Fig. 7b);
wherein the first semiconductor region and the second semiconductor region together form a PN-junction (Fig. 7b, element 108, paragraph 0063),
wherein the first conductive contact forms a Schottky contact (paragraph 0069 discloses first conductive contact comprising metal thereby forming metal semiconductor junction) with the second semiconductor region, and
wherein the semiconductor device includes a Schottky diode (paragraph 0069 discloses first and second conductive contact comprising metal thereby forming Schottky contact (metal semiconductor junction)).
Bowman does not explicitly disclose an epitaxial second semiconductor region.
However, since the first semiconductor region is an epitaxial region (paragraph 0063), it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to form the second semiconductor region with an epitaxial growth method with the motivation to improve conduction current.
Regarding claim 2, Bowman et al. teach wherein the epitaxial layer is of the first conductivity type (paragraph 0063), and wherein the second semiconductor region is formed as a blanket-implant region in the epitaxial layer (paragraph 0063).
Regarding claim 3, Bowman et al. teach wherein the epitaxial layer comprises: a first epitaxial layer (Fig. 7b, element 104, paragraph 0063) of the first conductivity type arranged on top of the substrate, wherein the first epitaxial layer forms the first semiconductor region; and a second epitaxial layer (Fig. 7b, element 106, paragraph 0063, since the first semiconductor region is an epitaxial region (paragraph 0063), it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to form the second semiconductor region with an epitaxial growth method with the motivation to improve conduction current) of the second conductivity type arranged on top of the first epitaxial layer, wherein the second epitaxial layer forms the second semiconductor region.
Regarding claim 4, Bowman et al. teach wherein the semiconductor device further comprises electrically insulating material (Fig. 7b, element 114, paragraph 0066) arranged inside the trench; and wherein the electrically insulating material comprises at least one material selected from the group consisting of Silicon Oxide, Silicon Nitride, and undoped polysilicon.
Regarding claim 6, Bowman et al. teach wherein the trench is formed as a closed-loop shape surrounding the inner portion, and wherein the trench is arranged closer to a periphery of the semiconductor body than to a center of the semiconductor body (Fig. 7b).
Regarding claim 7, Bowman et al. teach wherein the epitaxial layer comprises: a first epitaxial layer (Fig. 7b, element 104, paragraph 0063) of the first conductivity type arranged on top of the substrate, wherein the first epitaxial layer forms the first semiconductor region; and a second epitaxial layer (Fig. 7b, element 106, paragraph 0063, since the first semiconductor region is an epitaxial region (paragraph 0063), it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to form the second semiconductor region with an epitaxial growth method with the motivation to improve conduction current) of the second conductivity type arranged on top of the first epitaxial layer, wherein the second epitaxial layer forms the second semiconductor region.
Regarding claim 8, Bowman et al. teach wherein the semiconductor device further comprises electrically insulating material (Fig. 7b, element 114, paragraph 0066) arranged inside the trench, and wherein the electrically insulating material comprises at least one material selected from the group consisting of Silicon Oxide, Silicon Nitride, and undoped polysilicon.
Regarding claim 10, Bowman et al. teach wherein the trench is formed as a closed-loop shape surrounding the inner portion, and wherein the trench is arranged closer to a periphery of the semiconductor body than to a center of the semiconductor body (Fig. 7b).
Regarding claim 11, Bowman et al. teach wherein the trench is completely filled with the electrically insulating material (Fig. 7b, paragraph 0066).
Claims 5, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Bowman et al. (US 2015/0123240) in view of Ni et al. (CN 103840013).
Regarding claim 5, Bowman et al. teach all of the limitations as discussed above.
Bowman et al. do not explicitly disclose wherein the trench fully extends through both the first semiconductor region and the second semiconductor region, and the trench has a depth, taken in the first direction, that is greater than a width of the trench, taken in a second direction perpendicular to the first direction.
Ni et al. teach a semiconductor device comprising wherein the trench (Fig. 6, element 103, paragraph 0059) fully extends through both the first semiconductor region (Fig. 6, element 101, paragraph 0058) and the second semiconductor region (Fig. 6, element 102, paragraph 0061), and the trench has a depth, taken in the first direction, that is greater than a width of the trench, taken in a second direction perpendicular to the first direction (Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Bowman et al. according to the teachings of Ni et al. with the motivation to improve leakage current (paragraph 0018).
Regarding claim 9, Bowman et al. teach all of the limitations as discussed above.
Bowman et al. do not explicitly disclose wherein the trench fully extends through both the first semiconductor region and the second semiconductor region, and the trench has a depth, taken in the first direction, that is greater than a width of the trench, taken in a second direction perpendicular to the first direction.
Ni et al. teach a semiconductor device comprising wherein the trench (Fig. 6, element 103, paragraph 0059) fully extends through both the first semiconductor region (Fig. 6, element 101, paragraph 0058) and the second semiconductor region (Fig. 6, element 102, paragraph 0061), and the trench has a depth, taken in the first direction, that is greater than a width of the trench, taken in a second direction perpendicular to the first direction (Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Bowman et al. according to the teachings of Ni et al. with the motivation to improve leakage current (paragraph 0018).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
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