Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18458614 filed on 8/30/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election with traverse of claims 1-18, 20 in the reply filed on 12/1/2025 is acknowledged.
Applicant’s arguments with respect to electing species I (Fig. 2A) in combination with species VI (Fig. 3D) is persuasive.
Claim 4 recites the limitation “the first silicide layer covers the first impurity region and partially overlaps the first region base well in the vertical direction” does not appear to read on the elected species.
Claim 7 recites the limitation “a first region intermediate well having the first conductivity type, within the first region base well, wherein the first impurity region is disposed on the first region intermediate well”. Fig. 3D of the elected species does not disclose both the first and second region having intermediate well.
Accordingly claims 1-3, 5-6, 8-18, 20 will be considered for examination.
Allowable Subject Matter
Claims 3, 6, 9, 20 are objected to as being dependent upon a rejected base claim (independent claims 1 & 17), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Cai et al. (US 2009/0108346).
With respect to dependent claim 3, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the base well has the first conductivity type, and in a plan view, the first separation region includes a boundary between the first portion of the base well and the second region base well”.
With respect to dependent claim 6, the cited prior art does not anticipate or make obvious, inter alia, the step of: “a dummy mask on an upper surface of the semiconductor substrate in the first separation region”.
With respect to dependent claim 9, the cited prior art does not anticipate or make obvious, inter alia, the step of: “an impurity concentration of the second region intermediate well is higher than an impurity concentration of the second region base well”.
With respect to dependent claim 20, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the circuit region includes a display driver integrated circuit (DDI), and the plurality of cells surround the DDI at an edge of the display drive chip”.
Claims 11-16 are allowed.
The following is an examiner' s statement of reasons for allowance:
Claims 11-16: The primary reason for the allowance of the claims is the inclusion of the limitation “a dummy gate structure on an upper surface of the semiconductor substrate, the dummy gate structure on a first separation region of the semiconductor substrate, the first separation region being between the first silicide layer and the second silicide layer”, in all of the claims in combination with the remaining features of independent claim 16.
Cai et al. (US 2009/0108346) teach an electrostatic discharge (ESD) device (paragraph 0037 discloses the capability to use the device for ESD protection) comprising: a semiconductor substrate (Fig. 5, elements 54, 56, 66, paragraph 0024), the semiconductor substrate including a base well substrate (Fig. 21, element 66), a first region (Fig. 5, elements p well 82 & 88, paragraph 0025, 0029) in the base well, and a second region (Fig. 5, elements 62, 64, 52, paragraph 0024) in the base well, the first region including a first region base well (Fig. 5, element 82) having a first conductivity type and a first impurity region (Fig. 21, element 88) having the first conductivity type on the first region base well, the second region being apart from the first region in a horizontal direction in the base well (Fig. 5), the second region including a second region base well (Fig. 5, element 62) having a second conductivity type, a second region intermediate well (Fig. 64) having the second conductivity type in the second region base well, and a second impurity region (Fig. 21, element 52) having the second conductivity type on the second region intermediate well, the second conductivity being opposite the first conductivity type (p vs n type); a first silicide layer (Fig. 5, silicide region 84, paragraph 0025) on the first impurity region, the first silicide layer at least partially overlapping the first impurity region in a vertical direction; and a second silicide layer (Fig. 5, silicide region 96, paragraph 0027) on the second impurity region and spaced apart from the first silicide layer in the horizontal direction, the second silicide layer at least partially overlapping the second impurity region in the vertical direction, wherein a first portion of the base well is located between the first region and the second region (Fig. 5), and at least a portion of the first portion of the base well is located in a first separation region of the semiconductor substrate between the first silicide layer and the second silicide layer (Fig. 5).
However, Cai et al. do not teach or render obvious the above-quoted features recited in independent claim 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 8, 10, 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cai et al. (US 2009/0108346).
Regarding independent claim 1, Cai et al. teach an electrostatic discharge (ESD) device (paragraph 0037 discloses the capability to use the device for ESD protection) comprising:
a semiconductor substrate (Fig. 5, elements 54, 56, 66, paragraph 0024), the semiconductor substrate including a base well substrate (Fig. 5, element 66),
a first region (Fig. 5, elements 82 & 88, paragraph 0025, 0029) in the base well, and
a second region (Fig. 5, elements 62, 64, 52, paragraph 0024) in the base well,
the first region including a first region base well (Fig. 5, element 82) having a first conductivity type and a first impurity region (Fig. 21, element 88) having the first conductivity type on the first region base well,
the second region being apart from the first region in a horizontal direction in the base well (Fig. 5), the second region including a second region base well (Fig. 5, element 62) having a second conductivity type, a second region intermediate well (Fig. 64) having the second conductivity type in the second region base well, and a second impurity region (Fig. 21, element 52) having the second conductivity type on the second region intermediate well,
the second conductivity being opposite the first conductivity type (p vs n type);
a first silicide layer (Fig. 5, silicide region 84, paragraph 0025) on the first impurity region, the first silicide layer at least partially overlapping the first impurity region in a vertical direction; and
a second silicide layer (Fig. 5, silicide region 96, paragraph 0027) on the second impurity region and spaced apart from the first silicide layer in the horizontal direction, the second silicide layer at least partially overlapping the second impurity region in the vertical direction,
wherein a first portion of the base well is located between the first region and the second region (Fig. 5), and at least a portion of the first portion of the base well is located in a first separation region of the semiconductor substrate between the first silicide layer and the second silicide layer (Fig. 5).
Regarding claim 2, Cai et al. teach wherein the base well has the second conductivity type (Fig. 5, n type), and in a plan view, the first separation region includes a boundary between the first portion of the base well and the first region base well (Fig. 5 shows the boundary between element 66 and element 82).
Regarding claim 5, Cai et al. teach wherein the first silicide layer partially covers the first impurity region and is apart from a boundary of the first impurity region (Fig. 5), and the second silicide layer partially covers the second impurity region and is apart from a boundary of the second impurity region (Fig. 5).
Regarding claim 8, Cai et al. teach wherein the first impurity region is apart from a boundary of the first region base well, the second region intermediate well is apart from a boundary of the second region base well, and the second impurity region is apart from a boundary of the second region intermediate well (Fig. 5).
Regarding claim 10, Cai et al. teach wherein a conductivity type of the semiconductor substrate is different from a conductivity type of the base well (Fig. 5, p type substrate and n type base well).
Regarding independent claim 17, Cai et al. teach a display drive chip (This is an intended use recitation not structurally distinguishing from prior art) comprising:
a circuit region (Fig. 5, paragraph 0029 discloses LDMOS region 50);
an input region (Figs. 2 & 5, elements 42 & 44, paragraph 0022, 0029); and
an output region (Figs. 2 & 5, element 30 connected to common node 38, paragraph 0022) including a plurality of cells,
wherein the plurality of cells include an electrostatic discharge (ESD) device (paragraph 0037 discloses the capability to use the device for ESD protection), the ESD device includes
a P-type semiconductor substrate (Fig. 5, elements 54, 56, 66, paragraph 0024 disclose 54 comprising p type),
a base well (Fig. 5, element 66, paragraph 0024) having N-type in the P-type semiconductor substrate,
a first region (Fig. 5, elements 82 & 88, paragraph 0025, 0029) in the base well,
a second region (Fig. 5, elements 62, 64, 52, paragraph 0024) in the base well,
a first silicide layer (Fig. 5, silicide region 84, paragraph 0025), and
a second silicide layer (Fig. 5, silicide region 96, paragraph 0027),
the first region includes a first region base well Fig. 5, element 82) having a first conductivity type and a first impurity region Fig. 5, element 88) having the first conductivity type on the first region base well,
the second region is apart from the first region in a horizontal direction in the base well (Fig. 5), the second region includes a second region base well (Fig. 5, element 62) having a second conductivity type, a second region intermediate well (Fig. 5, element 64) having the second conductivity type in the second region base well, and a second impurity region (Fig. 5, element 52) having the second conductivity on the second region intermediate well,
the second conductivity type is opposite the first conductivity type ( p vs n type);
the first silicide layer is on the first impurity region, the first silicide layer at least partially overlaps the first impurity region in a vertical direction (Fig. 5),
the second silicide layer is on the second impurity region and spaced apart from the first silicide layer in the horizontal direction, the second silicide layer at least partially overlaps the second impurity region in the vertical direction (Fig. 5),
a portion of the base well is between the first region and the second region 9Fig. 5), and the portion of the base well is exposed to an upper surface of the P-type semiconductor substrate between the first silicide layer and the second silicide layer (Fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Cai et al. (US 2009/0108346).
Regarding claim 18, Cai et al. teach wherein the ESD device has a bar-type structure in which the first silicide layer and the second silicide layer each extend in a first horizontal direction and are parallel to each other in a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction (Fig. 5, the shape is a matter of choice which a person skilled in the art would have found obvious absent persuasive evidence that the particular shape of the claimed limitation was significant, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813