CTFR 18/458,650 CTFR 81546 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al, US Patent Application Publication 2023/0062775 (as cited in previous Office Action) in view of We et al, WO2022/250821 (newly submitted) Regarding claim 1, Hsu teaches a substrate comprising: a core layer 112 comprising a cavity ( 118, figure 1D ); an embedded passive device 600 located at least partially in the cavity of the core layer, wherein the embedded passive device comprises a plurality of pad interconnects 250s,250d, a polyimide layer 260 coupled to a surface of the embedded passive device [ 0032] ; a first plurality of via interconnects t11’ (M11, figure 1J and 1K) coupled to an touching the plurality of pad interconnects 250s,d ; at least one dielectric layer 500,122F, 142F, 162F coupled to the core layer; and a plurality of interconnects M12, M13 located at least partially in the at least one dielectric layer, wherein the plurality of interconnects comprise a second plurality of via interconnects t12’ located at least partially in the at least one dielectric layer 142F , and wherein the second plurality of via interconnects are coupled to and touch the first plurality of via interconnects ( figure 1O ). Hsu fails to teach the first plurality of via interconnects are located at least partially in the polyimide layer. However, We teaches that the polyimide layer 182 may also be used as a barrier to protect the via interconnects 184 as well as the pad interconnect 185 from unwanted contamination ( see figure 1 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of We with that of Hsu because it is generally-known in the art that the polyimide layer may also be used as a barrier to protect the via interconnects as well as the pad interconnect from unwanted contamination, thereby improving the electronic device. Regarding claim 2, Hsu teaches the at least one dielectric layer includes a different material ( silicon oxide or silicon nitride, [ 0042 ]) from the polyimide layer [ 0032 ]. Regarding claim 3, We teaches wherein the first plurality of via interconnects 184 touch the at least one dielectric layer 110 and the polyimide layer 182 , and wherein a first via interconnect from the first plurality of via interconnects comprises a first width ( measured from left to right side surfaces of 184 ), wherein a second via interconnect 126a from the second plurality of via interconnects comprises a second width ( measured from left to right of side surfaces of 126a ) that is greater than the first width (figure 1). Regarding claim 4, Hsu teaches the polyimide layer is coupled to a surface of the embedded passive device comprising the plurality of pad interconnects wherein the first plurality of via interconnects and the second plurality of via interconnects form a plurality of stacked via interconnects that are coupled to and touch the plurality of pad interconnects ( figure 1O ). Regarding claim 5, Hsu teaches the embedded passive device includes an integrated passive device (IPD) [ 0020 ]. Regarding claim 6, Hsu teaches the embedded passive device includes a deep trench capacitor [ 0028 ] Regarding claim 7, Hsu teaches the plurality of interconnects are configured to be electrically coupled to the embedded passive device, and wherein the polyimide layer vertically overlaps with the embedded passive device but does not vertically overlap with the core layer ( figure 1O ). Regarding claim 8, Hsu teaches at least one dielectric layer 500, 122R is located in at least part of the cavity of the core layer, and wherein the at least one dielectric layer touches (i) a top surface of the polyimide layer, (ii) a side surface of the polyimide layer and (iii) a side surface of the embedded passive device ( figure 1O ) Regarding claim 9, Hsu teaches the at least one dielectric layer laterally surrounds and touch the embedded passive device ( figure 1O ) Regarding claim 10, We teaches the substrate is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device , a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer , a computer , a wearable device , a laptop computer, a server , an internet of things (IoT) device, and a device in an automotive vehicle [0097] Regarding claim 11, Hsu teaches a package comprising: an integrated device 191 ; and a substrate coupled to the integrated device, wherein the substrate comprises: a core layer 112 comprising a cavity ( 118, figure 1D ); an embedded passive device 600 located at least partially in the cavity of the core layer, wherein the embedded passive device comprises a plurality of pad interconnects 250s,250d ; a polyimide layer 260 coupled to a surface of the embedded passive device [ 0032 ]; at least one dielectric layer 500, 122 coupled to the core layer; and a plurality of interconnects t11’, M11 located at least partially in the at least one dielectric layer wherein the plurality of interconnects comprise a first plurality of via interconnects t11’ located at least partially in (i) the at least one dielectric layer, wherein the first plurality of via interconnects touch (i) the at least one dielectric layer, and wherein the first plurality of via interconnects are coupled to and touch the plurality of pad interconnects of the embedded passive device. ( figure 1O) . Hsu fails to teach the first plurality of via interconnects located at least partially in (ii) the polyimide layer, wherein the first plurality of via interconnects touch (ii) the polyimide layer. However, We teaches that the polyimide layer 182 may also be used as a barrier to protect the via interconnects 184 as well as the pad interconnect 185 from unwanted contamination ( see figure 1 ), thereby meeting the limitations of “the first plurality of via interconnects located at least partially in (ii) the polyimide layer, wherein the first plurality of via interconnects touch (ii) the polyimide layer” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of We with that of Hsu because it is generally-known in the art that the polyimide layer may also be used as a barrier to protect the via interconnects as well as the pad interconnect from unwanted contamination, thereby improving the electronic device. Regarding claim 12, Hsu teaches the at least one dielectric layer includes a different material ( silicon oxide or silicon nitride, [ 0042 ]) from the polyimide layer [ 0032 ]. . Regarding claim 13, Hsu teaches the polyimide layer vertically overlaps with the embedded passive device but does not vertically overlap with the core layer ( figure 1O ) Regarding claim 14, Hsu teaches the polyimide layer is coupled to a surface of the embedded passive device comprising the plurality of pad interconnects and wherein the at least one dielectric layer 500, 122 touches (i) a top surface of the polyimide layer, (ii) a side surface of the polyimide layer and (iii) a side surface of the embedded passive device ( figure 1O ). Regarding claim 15, Hsu teaches the embedded passive device includes an integrated passive device (IPD) [ 0020 ]. Regarding claim 16, Hsu teaches the embedded passive device 112a includes a deep trench capacitor [ 0028 ] Regarding claim 17, Hsu teaches the plurality of interconnects are configured to be electrically coupled to the embedded passive device ( figure 1O ) Regarding claim 18, Hsu teaches the at least one dielectric layer is located in at least part of the cavity of the core layer ( figure 1O ) Regarding claim 19, Hsu teaches at least one dielectric layer laterally surrounds and touch the embedded passive device ( figure 1O ) Regarding claim 10, We teaches the package is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device , a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer , a computer , a wearable device , a laptop computer, a server , an internet of things (IoT) device, and a device in an automotive vehicle [0097] Regarding claim 21, Hsu teaches a method for fabricating a substrate, comprising: providing a core layer 112 forming a plurality of interconnects 116 in the core layer and on surfaces of the core layer; forming a cavity 118 in the core layer; providing an embedded passive device 600 in the cavity of the core layer, wherein the embedded passive device includes a plurality of pad interconnects 250 ; and a polyimide layer 260 [0032] ; forming at least one dielectric layer 500, 122 coupled to (i) the core layer and (ii) the embedded passive device; and forming a plurality of interconnects t11’, M11 located at least partially in the at least one dielectric layer, wherein forming the plurality of interconnects includes forming a plurality of via interconnects t11’ coupled to and touching the plurality of pad interconnects 250s,250d , and wherein the plurality of via interconnects extend through part of the at least one dielectric layer and the polyimide layer, wherein the plurality of via interconnects touch (i) the at least one dielectric layer ( figure 1O ). Hsu fails to teach the plurality of via interconnects touch (ii) the polyimide layer. However, We teaches that the polyimide layer 182 may also be used as a barrier to protect the via interconnects 184 as well as the pad interconnect 185 from unwanted contamination ( see figure 1 ), thereby meeting the limitation of “the plurality of via interconnects touch (ii) the polyimide layer”. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of We with that of Hsu because it is generally-known in the art that the polyimide layer may also be used as a barrier to protect the via interconnects as well as the pad interconnect from unwanted contamination, thereby improving the electronic device. Regarding claim 22, Hsu teaches the at least one dielectric layer ( silicon oxide or silicon nitride, [ 0042 ]) includes a different material from the polyimide layer [ 0032 ]. Regarding claim 23, Hsu teaches the polyimide layer vertically overlaps with the embedded passive device but does not vertically overlap with the core layer (figure 1O). Regarding claim 24, Hsu teaches the polyimide layer is coupled to a surface of the embedded passive device comprising the plurality of pad interconnects 250s, 250d a nd wherein the at least one dielectric layer 500, 122F touches (i) a top surface of the polyimide layer, (ii) a side surface of the polyimide layer and (iii) a side surface of the embedded passive device (figure 1O). Regarding claim 25, Hsu teaches the embedded passive device includes an integrated passive device (IPD) and/or a deep trench capacitor [ 0020 ]. Response to Arguments Applicant’s arguments with respect to claim(s) 1-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. 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QVJ /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/458,650 Page 2 Art Unit: 2899 Application/Control Number: 18/458,650 Page 3 Art Unit: 2899 Application/Control Number: 18/458,650 Page 4 Art Unit: 2899 Application/Control Number: 18/458,650 Page 5 Art Unit: 2899 Application/Control Number: 18/458,650 Page 6 Art Unit: 2899 Application/Control Number: 18/458,650 Page 7 Art Unit: 2899 Application/Control Number: 18/458,650 Page 8 Art Unit: 2899 Application/Control Number: 18/458,650 Page 9 Art Unit: 2899 Application/Control Number: 18/458,650 Page 10 Art Unit: 2899 Application/Control Number: 18/458,650 Page 11 Art Unit: 2899 Application/Control Number: 18/458,650 Page 12 Art Unit: 2899
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