DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu et al (US Publication no. 2022/0262785).
Regarding claim 1, Yu discloses a semiconductor integrated circuit device, comprising a circuit block including first and second standard cells Fig 7, wherein the first standard cell includes a first buried power line Fig 7, PL71 extending in a first direction and supplying first power Fig 7, and a first transistor of a first conductivity type ¶0046, 0056-0057, 0064, the first transistor is supplied with the first power from the first buried power line Fig 7, the second standard cell includes a second buried power line Fig 7, PL72 extending in the first direction and supplying the first power, an upper-layer power line Fig 7, PL63 formed in a layer above the second buried power line Fig 7, PL72 and located to overlap the second buried power line in planar view Fig 7, the upper-layer power line supplying second power ¶0062-0067, and a second transistor of the first conductivity type¶0046, 0056-0057, 0064, and the second transistor is supplied with the second power from the upper-layer power line ¶0061- 0064.
Regarding claim 2, Yu discloses wherein the first and second standard cells are adjacent to each other in the first direction Fig 7, and the first buried power line and the second buried power line are formed continuously in the first direction Fig 7.
Regarding claim 9, Yu discloses wherein the circuit block includes a second upper-layer power line placed above the upper-layer power line to extend in a second direction perpendicular to the first direction, and the upper-layer power line is electrically connected to the second upper-layer power line Fig 7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US Publication no. 2022/0262785) in view of Azmat et al (US Publication No. 2020/0057830).
Regarding claim 3, Yu discloses all the limitations but is silent on having a well.
Whereas Azmat discloses wherein the second standard cell includes a well of a second conductivity type, and a well tap configured to supply a potential to the well, the second transistor is formed on the well, and the well tap is electrically connected to the upper-layer power line Fig 5.
Yu and Azmat are analogous art because they are directed to semiconductor devices having specific power line arrangements and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Yu and incorporate the teachings of Azmat to address noise related concerns and control body potential of the transistors.
Regarding claim 4, Yu discloses all the limitations but is silent on whether the second standard cell is a double-height cell, and the second buried power line and the upper-layer power line are placed in a center portion of the second standard cell in a second direction perpendicular to the first direction.
Azmat discloses wherein the second standard cell is a double-height cell, and the second buried power line and the upper-layer power line are placed in a center portion of the second standard cell in a second direction perpendicular to the first direction Fig 9.
Yu and Azmat are analogous art because they are directed to semiconductor devices having specific power line arrangements and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Yu and incorporate the teachings of Azmat to provide an alternative layout as a matter of design choice.
Regarding claim 5, Yu discloses all the limitations but is silent on whether the second standard cell includes a third transistor of the first conductivity type, the third transistor is supplied with the second power from the upper-layer power line, and the second and third transistors are placed on opposite sides of the upper-layer power line in the second direction.
Azmat discloses wherein the second standard cell includes a third transistor of the first conductivity type, the third transistor is supplied with the second power from the upper-layer power line, and the second and third transistors are placed on opposite sides of the upper-layer power line in the second direction Fig 8A-9.
Yu and Azmat are analogous art because they are directed to semiconductor devices having specific power line arrangements and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Yu and incorporate the teachings of Azmat to provide an alternative layout as a matter of design choice.
Regarding claim 8, Yu discloses wherein the second standard cell includes a third transistor of the first conductivity type, and the third transistor is supplied with the first power from the second buried power line Fig 7.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US Publication no. 2022/0262785) in view of Azmat et al (US Publication No. 2020/0057830) and in further view of Oh (US Publication No. 2017/0069660).
Regarding claims 6 and 7, Yu discloses all the limitations but silent on the buffer circuit.
Whereas Oh discloses wherein the second standard cell includes a buffer circuit configured to transmit a single signal, and the buffer circuit includes the second and third transistors ¶0050-0058 Fig 2, 4-6 and wherein the second standard cell includes first and second buffer circuits configured to transmit mutually independent signals, the first buffer circuit includes the second transistor, and the second buffer circuit includes the third transistor¶0050-0058 Fig 2, 4-6.
Yu, Azmat, and Oh are analogous art because they are directed to semiconductor devices having specific power line arrangements and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Yu and incorporate the teachings of Oh to improve device performance.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811