DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election Requirement filed 04 March 2026. Claims 1-20 are pending in this application. Claims 12-20 are withdrawn from consideration, and Claims 1-11 are examined in this Office Action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 04 March 2026 is acknowledged. The traversal is on the ground(s) that there is no serious search burden. This is not found persuasive for the reasons listed in the Restriction Requirement.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 4, Claim 4 list materials for the carbon-based material (line 2), the semiconducting oxide (lines 3-4) and the metal chalcogenide (Lines 4-5). However, Claim 3, from which Claim 4 depends only requires the semiconductor material to contain “at least one selected from the group consisting of a hexagonal boron nitride, a carbon-based material, a semiconducting oxide and a metal chalcogenide”. Claim 4 is not listed in the alternative, so Claim 4 makes it seem as if all three materials are required at the same time. This contradicts Claim 3 which requires only one material for the SD semiconductor material. It is unclear whether Claim 4 is meant to require all the listed materials simultaneously, or whether they are meant to be listed in the alternative.
For purposes of examination, Claim 4 will be interpreted to require only one of the conditions listed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6-7, 9 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Chiang et. al (US 2024/0178228 A1)
Regarding Claim 1, Chiang discloses (as shown in Figs. 1A-C) A semiconductor device ([0022] PFET 100P), comprising:
a pair of channel structures ([0025] the PFET 100P include channel structures 106P) each configured to have a current direction along a first direction ([0026] a second lateral direction D2 intersected with (e.g., substantially perpendicular to) the first lateral direction D1) substantially parallel to a working surface of a substrate ([0031] Referring to FIG. 1B and FIG. 1C, the PFET 100P and the NFET 100N are built on a semiconductor substrate 110, such as a silicon wafer.); ([0026] the channel structures 106P may extend along a second lateral direction D2)
source/drain (S/D) structures ([0024] the source/drain contacts 104P) on opposing sides of the pair of channel structures (106P) along the first direction; (See Fig. 1A, showing the source/drain contacts 104P on opposing dies of the channel structures 106P in the D2 direction)
and a gate structure ([0025] gate structure 102P) between the pair of channel structures (106P), (See Fig. 1B, showing the gate 102P fills the space between the channel structures 106P)
wherein the pair of channel structures (106P) comprises two-dimensional (2D) semiconductor material oriented ([0025] The channel structures 106P are formed of a semiconducting material, such as crystalline silicon. Further, the channel structures 106P are formed as thin walls, each resemble a vertical two-dimensional structure) substantially perpendicular to the working surface of the substrate (110). ([0026] Further, the major sidewalls W 106P of the channel structures 106P may span along the second lateral direction D2 and a substantially vertical direction D3)
Regarding Claim 6, Chiang further discloses (as shown in Fig. 1C) a pair of inner spacers ([0034] a sidewall spacer 122P) positioned on opposing sides of the gate structure along the first direction and each positioned between the gate structure (102P) and a respective S/D structure of the S/D structures (104P). ([0034] a sidewall spacer 122P is provided along opposite sides of the gate structure 102P, for ensuring electrical isolation between the gate structure 102P and the source/drain contacts 104P.)
Regarding Claim 7, Chiang further discloses (as shown in Fig. 1A-C) wherein: the gate structure (102P) comprises a gate metal ([0032] The gate structure 102P may include a gate electrode 114P) and a pair of gate dielectrics, and the pair of gate dielectrics ([0032] gate dielectric layers 116P separating the channel structures 106P from the gate electrode 114P) are positioned on opposing sides of the gate metal (114P) in a second direction substantially parallel to the working surface of the substrate (110). See Fig. 1B, showing the gate dielectric 116P on opposite sides of the portions of the gate electrode 114P between the channel structures 106P)
Regarding Claim 9, Chiang further discloses (as shown in Fig. 1A-C) the pair of channel structures (106P) each has a shape of a nanosheet ([0025] Further, the channel structures 106P are formed as thin walls, each resemble a vertical two-dimensional structure and have major sidewalls W 106p being (110) crystalline planes) extending substantially perpendicular to the working surface of the substrate (110). ([0026] Further, the major sidewalls W 106P of the channel structures 106P may span along the second lateral direction D2 and a substantially vertical direction D3.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang as applied to claim 1 above, and further in view of O’Brien et. al (US 2023/0097898 A1)
Regarding Claim 2, Chiang fails to disclose the pair of channel structures each includes one or more monolayers of the 2D semiconductor material, the one or more monolayers stacked in a second direction substantially parallel to the working surface of the substrate.
O’Brien discloses (as shown in Fig. 1) the channel structures ([0023] monolayers 110) each includes one or more monolayers of the 2D semiconductor material ([0023] In embodiments, each of the monolayers 110 may be made up of a single monolayer. In other embodiments, each of the monolayers 110 may be multiple monolayers that are stacked on top of each other.),
O’Brien teaches that as silicon thickness becomes very thin, mobility decreases resulting in defective transistors. ([0010] a silicon thickness that is too thin may cause a mobility decrease and result in a defective transistor.) O’Brien further teaches that using monolayers allows the distance between layers to be reduced, thereby increasing the number of layers in the gate structure. ([0012] In embodiments, by using one or more monolayers within a gate structure, distances between layers may be reduced to 6 nm or less, which may also allow an increase in the number of monolayers within the gate structure.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use the monolayers of O’Brien instead of the silicon nanosheets of Chiang in order to decrease the distance between layers without decreasing mobility.
However, O’Brien fails to disclose the one or more monolayers stacked in a second direction substantially parallel to the working surface of the substrate.
Chiang teaches the silicon nanosheets are oriented perpendicular to the substrate ([0026] Further, the major sidewalls W 106P of the channel structures 106P may span along the second lateral direction D2 and a substantially vertical direction D3). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application for the layers of the monolayers of O’Brien would be stacked in a direction parallel to the surface of the substrate in the transistor of Chiang.
Regarding Claim 3, Chiang fails to disclose wherein: the 2D semiconductor material includes at least one selected from the group consisting of a hexagonal boron nitride, a carbon-based material, a semiconducting oxide and a metal chalcogenide.
O’Brien discloses (as shown in Fig. 4) wherein: the 2D semiconductor material includes at least one selected from the group consisting of a hexagonal boron nitride, a carbon-based material, a semiconducting oxide and a metal chalcogenide. ([0029] a monolayer 406 may be applied, which may also be referred to as a 2D Transition Metal Dichalcogenide (TMD))
O’Brien teaches that as silicon thickness becomes very thin, mobility decreases resulting in defective transistors. ([0010] a silicon thickness that is too thin may cause a mobility decrease and result in a defective transistor.) O’Brien further teaches that using monolayers allows the distance between layers to be reduced, thereby increasing the number of layers in the gate structure. ([0012] In embodiments, by using one or more monolayers within a gate structure, distances between layers may be reduced to 6 nm or less, which may also allow an increase in the number of monolayers within the gate structure.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use the monolayers of O’Brien instead of the silicon nanosheets of Chiang in order to decrease the distance between layers without decreasing mobility.
Regarding Claim 4, O’Brien further discloses (as shown in Fig. 3) wherein: the carbon-based material includes graphene, the semiconducting oxide includes at least one selected from the group consisting of ZnO, CdO and In203, and the metal chalcogenide includes at least one selected from the group consisting of WS2, WSe2, WTe2, MoS2, MoSe2, MoTe2, HfS2, ZrS2, TiS2, GaSe, InSe, SnS and TiS3. ([0027] In embodiments, there may be plurality of monolayers that have a tri-layer stack or other layer stack that may include MoS.sub.2, WS.sub.2, or MoS.sub.2.)
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang as applied to claim 9 above, and further in view of O’Brien et. al (US 2023/0097898 A1).
Regarding Claim 10, Chiang fails to disclose wherein: the nanosheet has a first dimension of 1-15 nm in the first direction, the nanosheet has a second dimension of 0.1-3.0 nm in a second direction substantially parallel to the working surface of the substrate, and the nanosheet has a third dimension of 1-15 nm in a third direction substantially perpendicular to the working surface of the substrate.
O’Brien discloses (as shown in Fig. 1, 4C) wherein: the nanosheet has a first dimension of 1-15 nm in a first direction, ([0100] Example 14 includes the method of example 12, wherein a distance along the first side of the monolayer between the surface of the first contact metal and the surface of the second contact metal is less than or equal to 15 nm.)
the nanosheet has a second dimension of 0.1-3.0 nm in a second direction, ([0103] Example 17 includes the method of any one of examples 12-15, wherein the monolayer has a thickness of 3.3 angstroms (Å).)
and the nanosheet has a third dimension of 1-15 nm in a third ([0032] In embodiments, the width 491 of the resulting cell 490 may be between 10 nm and 100 nm)
O’Brien teaches that as silicon thickness becomes very thin, mobility decreases resulting in defective transistors. ([0010] a silicon thickness that is too thin may cause a mobility decrease and result in a defective transistor.) O’Brien further teaches that using monolayers allows the distance between layers to be reduced, thereby increasing the number of layers in the gate structure. ([0012] In embodiments, by using one or more monolayers within a gate structure, distances between layers may be reduced to 6 nm or less, which may also allow an increase in the number of monolayers within the gate structure.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use the monolayers of O’Brien instead of the silicon nanosheets of Chiang in order to decrease the distance between layers without decreasing mobility.
However, O’Brien fails to disclose the second direction is substantially parallel to the working surface of the substrate
And the third direction is substantially perpendicular to the working surface of the substrate.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application for the combination of Chiang and O’Brien to have the second direction is substantially parallel to the working surface of the substrate and the third direction is substantially perpendicular to the working surface of the substrate. In O’Brien, the second direction is the thickness of the nanosheet ([0103] Example 17 includes the method of any one of examples 12-15, wherein the monolayer has a thickness of 3.3 angstroms (Å).). In Chiang the thickness of the nanosheet (106P) extends parallel to the substrate (110). (See Fig. 1) Therefore, the second direction (thickness direction) in Chiang in view of O’Brien would be parallel to the working surface of the substrate (110). In O’Brien, the third direction is the width of the nanosheet (See Fig. 4C). In Chiang, this width direction is perpendicular to the substrate. ([0026] Further, the major sidewalls W 106P of the channel structures 106P may span … a substantially vertical direction D3) Therefore, the third direction (width direction) in Chiang in view of O’Brien would be perpendicular to the working surface of the substrate (110).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of O’Brien as applied to claim 10 above, and further in view of Basker et. al (US 9.455.317 B1)
Regarding Claim 11, O’Brien further discloses (as shown in Fig. 1, 4C) wherein: a first ratio of the second dimension ([0103] Example 17 includes the method of any one of examples 12-15, wherein the monolayer has a thickness of 3.3 angstroms (Å).) to the first dimension ([0100] Example 14 includes the method of example 12, wherein a distance along the first side of the monolayer between the surface of the first contact metal and the surface of the second contact metal is less than or equal to 15 nm.) is 0.05-0.3, (.33 nm/ <15 nm is >.022 which overlaps the claimed range)
However, O’Brien fails to disclose a second ratio of the second dimension ([0103] Example 17 includes the method of any one of examples 12-15, wherein the monolayer has a thickness of 3.3 angstroms (Å).) to the third dimension ([0032] In embodiments, the width 491 of the resulting cell 490 may be between 10 nm and 100 nm) is 0.05-0.3. (.33 nm/ 10 nm is .033 nm for the largest ratio)
Basker discloses (as shown in Fig. 10) third dimension is between 6nm and 12 nm ([Col. 3 Lines 48-50] According to a non-limiting embodiment, the fins 108 have a width (e.g., along the Y-axis) ranging from approximately 6 nm to approximately 12 nm)
Basker teaches a smaller third dimension (width) than O’Brien. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have a smaller third dimension (width in O’Brien and Basker) in order to minimize the footprint of the transistor.
The second ratio would thus become the ratio of the second dimension (thickness) in O’Brien and the third dimension (width) in Basker. This ratio is between 0.055 (.33 nm/6 nm) and .0275 (.33 nm/12 nm). This range overlaps the claimed range.
Allowable Subject Matter
Claim 5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 5, Chiang fails to disclose wherein: the gate structure (102P) is fully surrounded by an enclosure formed of the pair of channel structures (106P) and the S/D structures (104P) in a horizontal plane substantially parallel to the working surface of the substrate (110).
Because the prior art is missing some of the limitations of Claim 5, Claim 5 contains allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gardner et. al (US 2023/0108707 A1).
Regarding Claim 10, Chiang fails to disclose wherein: the nanosheet has a first dimension of 1-15 nm in the first direction, the nanosheet has a second dimension of 0.1-3.0 nm in a second direction substantially parallel to the working surface of the substrate, and the nanosheet has a third dimension of 1-15 nm in a third direction substantially perpendicular to the working surface of the substrate.
Gardner discloses (as shown in Fig. 9) the nanosheet has a first dimension of 1-15 nm in the first direction, ([0040] The surface areas of the surfaces of the carrier nanosheet 115 can be defined by the sizes of its length, width and thickness any combination of which can provide surface area for 2D channels 250. For example, carrier nanosheet 115 can include a thickness whose size in relation to the size of the length of the carrier nanosheet 115 can be up to 1/16, ⅛, ¼, ⅓, ½, 1 or 1.5, 2, 4, 8 or 16 times the length of the carrier nanosheet 115.) ([0045] Nanosheet 115 layer can have any thickness that provides sufficient structural support for the 2D material 110 for the steps of the fabrication and use, including for example a thickness that is up to 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18 or 20 nm.)
the nanosheet has a second dimension of 0.1-3.0 nm in a second direction ([0033] 2D material 110 layer can, depending on the material and design, and can have a broader range of thicknesses, such as between 0.2 nm and 3.0 nm, for example.)
and the nanosheet has a third dimension of 1-15 nm in a third direction substantially perpendicular to the working surface of the substrate. ([0040] The surface areas of the surfaces of the carrier nanosheet 115 can be defined by the sizes of its length, width and thickness any combination of which can provide surface area for 2D channels 250. For example, carrier nanosheet 115 can include a thickness whose size in relation to the size of the length of the carrier nanosheet 115 can be up to 1/16, ⅛, ¼, ⅓, ½, 1 or 1.5, 2, 4, 8 or 16 times the length of the carrier nanosheet 115. Similarly, the width of the carrier nanosheet 115 can have a size that in relation to the size of the length of the carrier nanosheet can be up to 1/16, ⅛, ¼, ⅓, ½, 1 or 1.5, 2, 4, 8 or 16 times the length of the carrier nanosheet 115) ([0045] Nanosheet 115 layer can have any thickness that provides sufficient structural support for the 2D material 110 for the steps of the fabrication and use, including for example a thickness that is up to 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18 or 20 nm.)
Claim Interpretation Note: The disclosed ranges encompass the claimed ranges. Therefore, the claimed ranges would be obvious.
Gardner teaches that 2D channel materials allow for further scaling down of transistors, thereby improving performance. ([0005] The solution provided herein addresses the short-channel effect and other similar problems by providing a transistor architecture that utilizes 2D material layers structurally supported by semiconductor nanosheets to form effective transistor channels that allow for continued performance improvement and scaling down of transistors.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use the 2D channel materials of Garner in Chiang in order to improve device performance.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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