DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
1. Claims 3-19, and 30-44 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/2/26. The Applicant has elected claims 9, 10, and 11 to be examined, but these claims depend from withdrawn claims, hence claims 9, 10, and 11 will be withdrawn also.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 20, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2022/0190071 Bae et al.
2. Referring to claim 1, Bae et al. teaches a backplane substrate of a display device comprising subpixels, (Figures 1-5 #SPX1-3), the backplane substrate comprising: a support substrate, (Figures 1-5 #SUB); a circuit layer, (Figures 1-5 #CCL), on a first surface of the support substrate, (Figures 1-5 #SUB), and comprising pixel drivers, (Figures 1-5 #T1), corresponding to the subpixels, (Figures 1-5 #SPX1-3), respectively; an electrode layer, (Figures 1-5 #RME1), on the circuit layer, (Figures 1-5 #CCL), and comprising an anode and a cathode, (Paragraph 0057 teaches an inorganic LED), corresponding to an emission area of each of the subpixels, (Figures 1-5 #SPX1-3); a bank layer, (Figures 1-5 #IBN1-2 & EBN), on the circuit layer, (Figures 1-5 #CCL), and corresponding to an area around the emission area of each of the subpixels, (Figures 1-5 #SPX1-3); and a valley, (Figures 1-5 valley area between #IBN1 & EBN and the area between IBN2 & EBN), spaced from edges of the support substrate, (Figures 1-5 #SUB), and penetrating at least the bank layer, (Figures 1-5 #IBN1-2 & EBN).
3. Referring to claim 2, Bae et al. teaches a backplane substrate of claim 1, wherein the display device further comprises pixels, (Figures 1-5 #PX), each comprising two or more adjacent subpixels, (Figures 1-5 #SPX1 & SPX2), from among the subpixels, (Figures 1-5 #SPX1-3), wherein the pixels comprise first pixels, (Figure 1-5 #PX closest to the edge of the support substrate), closest to the edges of the support substrate, (Figures 1-5 #SUB), and second pixels, (Figures 1-5 #PX adjacent to the edge pixel), adjacent to the first pixels, and wherein the valley, (Figures 1-5 valley area between #IBN1 & EBN and the area between IBN2 & EBN in the outer subpixel region of each pixel hence being a boundary between the adjacent pixel’s outer subpixel), is at a boundary between emission areas of the first pixels and emission areas of the second pixels and shaped similarly, (similarly is read in its broadest reasonable manner), to the edges of the support substrate.
4. Referring to claim 20, Bae et al. teaches a display device comprising: a backplane substrate comprising pixel drivers, (Figures 1-5 #T1), respectively corresponding to subpixels, (Figures 1-5 #SPX1-3), and an anode and a cathode, (Paragraph 0057 teaches an inorganic LED), corresponding to an emission area of each of the subpixels, (Figures 1-5 #SPX1-3); and light emitting elements, (Figures 1-5 #ED), respectively corresponding to the emission areas of the subpixels, (Figures 1-5 #SPX1-3), wherein each of the light emitting elements, (Figures 1-5 #ED), is mounted on the anode and the cathode, (Paragraph 0057 teaches an inorganic LED), of each of the subpixels, (Figures 1-5 #SPX1-3), wherein the backplane substrate, (Figures 1-5 #SUB), comprises: a support substrate, (Figures 1-5 #SUB); a circuit layer, (Figures 1-5 #CCL), on a first surface of the support substrate, (Figures 1-5 #SUB), and comprising the pixel drivers, (Figures 1-5 #T1); an electrode layer, (Figures 1-5 #RME1), on the circuit layer, (Figures 1-5 #CCL), and comprising the anode and the cathode, (Paragraph 0057 teaches an inorganic LED), of each of the subpixels, (Figures 1-5 #SPX1-3); a bank layer, (Figures 1-5 #IBN1-2 & EBN), on the circuit layer, (Figures 1-5 #CCL), and corresponding to an area around the emission area of each of the subpixels, (Figures 1-5 #SPX1-3); and a valley, (Figures 1-5 valley area between #IBN1 & EBN and the area between IBN2 & EBN), spaced from edges of the support substrate, (Figures 1-5 #SUB), and penetrating at least the bank layer, (Figures 1-5 #IBN1-2 & EBN).
5. Referring to claim 21, Bae et al. teaches a display device of claim 20, further comprises pixels, (Figures 1-5 #PX), each comprising two or more adjacent subpixels, (Figures 1-5 #SPX1 & SPX2), from among the subpixels, (Figures 1-5 #SPX1-3), wherein the pixels comprise first pixels, (Figure 1-5 #PX closest to the edge of the support substrate), closest to the edges of the support substrate, (Figures 1-5 #SUB), and second pixels, (Figures 1-5 #PX adjacent to the edge pixel), adjacent to the first pixels, and wherein the valley, (Figures 1-5 valley area between #IBN1 & EBN and the area between IBN2 & EBN in the outer subpixel region of each pixel hence being a boundary between the adjacent pixel’s outer subpixel), is at a boundary between emission areas of the first pixels and emission areas of the second pixels and shaped similarly, (similarly is read in its broadest reasonable manner), to the edges of the support substrate.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
6. Claims 22-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
7. The prior art teaches the claimed matter in the rejections above, but is silent with respect to the above teachings in combination with the display device of claim 21, wherein the circuit layer comprises: a semiconductor layer on the first surface of the support substrate; a first conductive layer on a first gate insulating layer covering the semiconductor layer; a second conductive layer on a second gate insulating layer covering the first conductive layer; a third conductive layer on an interlayer insulating layer covering the second conductive layer; a fourth conductive layer on a first planarization layer covering the third conductive layer; a fifth conductive layer on a second planarization layer covering the fourth conductive layer; and a third planarization layer covering the fifth conductive layer, wherein the electrode layer is on the third planarization layer, wherein the bank layer comprises a bank planarization layer on the circuit layer and a bank insulating layer covering the bank planarization layer, and wherein the bank insulating layer comprises an inorganic insulating material and extends to edges of the emission area of each of the subpixels and covers a portion of edges of the anode and a portion of edges of the cathode.
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication No 2019/0363146 Takahashi et al.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR A MANDALA whose telephone number is (571)272-1918. The examiner can normally be reached on M-Th 8-6:30 EST.
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/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 2/12/26