DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on 08/30/2023, 02/10/2025 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 12, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0183975 A1), hereafter “Lee”, and further in view of Kwon et al. (US 2014/0159037 A1), hereafter “Kwon”.
As to claim 1, Lee teaches a thin film transistor substrate comprising:
a substrate (Fig. 6, 610, ⁋ [0141]);
a first thin film transistor (Tr2, ⁋ [0141]) on the substrate, the first thin film transistor including a first gate electrode (⁋ [0143], 672), a first active layer (642), a first source electrode (683), and a first drain electrode (684); and
a second thin film transistor (Tr1, ⁋ [0141]) on the substrate, the second thin film transistor including a second gate electrode (671, ⁋ [0142]), a second active layer (641+643, ⁋ [0142]) with a pattern different from a pattern of the first active layer (first active layer contains 1 layer and second active layer contains 2), a second source electrode (682), and a second drain electrode (681), and
wherein the second active layer includes a second lower active layer (641) overlapping the second gate electrode (671) and a second upper active layer (643) on the second lower active layer and overlapping the second gate electrode (671).
Lee fails to teach wherein the first active layer includes a first lower active layer overlapping the first gate electrode and a first upper active layer on the first lower active layer and not overlapping the first gate electrode.
Kwon teaches a thin film transistor (⁋ [0096], “a thin film transistor”) with a lower active layer (Fig. 4B, 420B, ⁋ [0097]) overlapping the gate electrode (460B, ⁋ [0096]) and an upper active layer (430B/431B+432B) on the first lower active layer and not overlapping the gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the two active layer patterns as taught by Kwon into the thin film transistor of Lee as the two conductive members are arranged to decrease resistance between a channel region of the oxide semiconductor layer and the source and drain electrodes (⁋ [0010]).
As to claim 3, Lee in view of Kwon teaches the thin film transistor substrate according to claim 1, Kwon teaches further comprising: a gate insulating layer (⁋ [0096], 470B, Fig. 4B) between the first gate electrode (460B) and the first active layer (420B+430B), a first contact hole included in the gate insulating layer exposing the first upper active layer (Fig. 7D, ⁋ [0117], “a first contact hole and a second contact hole are formed in at least one of the first and second insulating layers”), and wherein the first upper active layer (430B) includes a first upper conductive part in a portion exposed by the first contact hole (⁋ [0097], “a conductive layer”).
As to claim 12, Lee in view of Kwon teaches the thin film transistor substrate according to claim 1, Lee teaches wherein the second lower active layer (641) includes a third channel part (Fig. 6, 641a, ⁋ [0165]) in a region overlapping the second gate electrode (671).
As to claim 16, Lee in view of Kwon teaches the thin film transistor substrate according to claim 1, Lee teaches wherein the first gate electrode (672) and the second gate electrode (671) are made of a same material on a same layer (⁋ [0171]).
Lee in view of Kwon fail to explicitly teach wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are made of a same material on a same layer, however, Lee does teach that 681-684 are source and drain electrodes (⁋⁋ [0176], [0179]).
It would have been obvious to one having ordinary skill in the art before the effective filing date to use the same material for all 4 electrodes of Lee, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
As to claim 17, Lee teaches a thin film transistor substrate comprising:
a substrate (Fig. 6, 610, ⁋ [0141);
a first thin film transistor (Tr2, ⁋ [0141]) on the substrate, the first thin film transistor including a first gate electrode (⁋ [0143], 672), a first active layer (642), a first source electrode (683), and a first drain electrode (684); and
a second thin film transistor (Tr1, ⁋ [0141]) on the substrate, the second thin film transistor including a second gate electrode (671, ⁋ [0142]), a second active layer (641+643, ⁋ [0142]) with a pattern different from a pattern of the first active layer (first active layer contains 1 layer and second active layer contains 2), a second source electrode (682), and a second drain electrode (681), and
wherein the second active layer includes a second lower active layer (641) and a second upper active layer (643) on the second lower active layer and having a same shape as the second lower active layer (Fig. 6 shows they both have the same shape).
Lee fails to teach wherein the first active layer includes a first lower active layer and two first upper active layers disposed to be spaced apart from each other on one side and another side of the first lower active layer.
Kwon teaches a thin film transistor (⁋ [0096], ”a thin film transistor”) with a lower active layer (Fig. 4B, 420B, ⁋ [0097]), and two upper active layers (430B/431B+432B) spaced apart from each other on each side of the first lower active layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the two active layer patterns as taught by Kwon into the thin film transistor of Lee as the two conductive members are arranged to decrease resistance between a channel region of the oxide semiconductor layer and the source and drain electrodes (⁋ [0010]).
Allowable Subject Matter
Claims 2, 4-10, 13, 15, and 18-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 2 Lee in view of Kwon are the closest prior art and fails to teach wherein the first lower active layer includes a same semiconductor material as the second lower active layer and is disposed on a same layer as the second lower active layer, and wherein the first upper active layer includes a same semiconductor material as the second upper active layer and is on the same layer as the second upper active layer.
As to claim 4 (from which 5 and 6 depend) Lee in view of Kwon are the closest prior art and fails to teach a first connection electrode on the gate insulating layer and coupled to the first upper conductive part, wherein the first connection electrode includes a same material as the first gate electrode.
As to claim 7 Lee in view of Kwon are the closest prior art and fails to teach wherein the first lower active layer includes a first channel part overlapping the first gate electrode, a first connection part overlapping the first upper active layer, and a first lower conductive part disposed between the first channel part and the first connection part.
As to claim 8 (from which 9-11 depend) Lee in view of Kwon are the closest prior art and fails to teach a gate insulating layer between the second gate electrode and the second active layer, wherein the gate insulating layer includes a second contact hole exposing the second upper active layer, and wherein the second upper active layer includes a second upper conductive part in a portion exposed by the second contact hole
As to claim 13 (from which 15 depends) Lee in view of Kwon are the closest prior art and fails to teach a first light shielding layer coupled to the first source electrode, disposed below the first active layer, and overlapping the first active layer.
As to claim 18 (from which 19 depends) Lee in view of Kwon are the closest prior art and fails to teach wherein the first lower active layer and the second lower active layer include a same semiconductor material, wherein the first upper active layer and the second upper active layer include a same semiconductor material, and wherein a carrier mobility of each of the first upper active layer and the second upper active layer is greater than a carrier mobility of each of the first lower active layer and the second lower active layer.
As to claim 20 (from which 21-23 depends) Lee in view of Kwon are the closest prior art and fails to teach a third upper conductive part between the second channel part and the second upper conductive part, and wherein the second lower active layer includes a third channel part overlapping the second gate electrode.
Conclusion
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/CARNELL HUNTER III/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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