DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on 04/24/2026 has been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Response to Arguments
The instant Non-Final Rejection replaces the previous Non-Final Rejection mailed on 02/24/2026.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0183975 A1), hereafter “Lee”, and further in view of Kwon et al. (US 2014/0159037 A1), hereafter “Kwon”.
As to claim 1, Lee teaches a thin film transistor substrate comprising:
a substrate (Fig. 6, 610, ⁋ [0141]);
a first thin film transistor (Tr2, ⁋ [0141]) on the substrate, the first thin film transistor including a first gate electrode (⁋ [0143], 672), a first active layer (642), a first source electrode (683), and a first drain electrode (684); and
a second thin film transistor (Tr1, ⁋ [0141]) on the substrate, the second thin film transistor including a second gate electrode (671, ⁋ [0142]), a second active layer (641+643, ⁋ [0142]) with a pattern different from a pattern of the first active layer (first active layer contains 1 layer and second active layer contains 2), a second source electrode (682), and a second drain electrode (681), and
wherein the second active layer includes a second lower active layer (641) overlapping the second gate electrode (671) and a second upper active layer (643) on the second lower active layer and overlapping the second gate electrode (671).
Lee fails to teach wherein the first active layer includes a first lower active layer overlapping the first gate electrode and a first upper active layer on the first lower active layer and not overlapping the first gate electrode, wherein the first lower active layer includes a same semiconductor material as the second lower active layer and is disposed on a same layer as the second lower active layer, and wherein the first upper active layer includes a same semiconductor material as the second upper active layer and is on the same layer as the second upper active layer.
Kwon teaches a thin film transistor (⁋ [0096], “a thin film transistor”) with a lower active layer (Fig. 4B, 420B, ⁋ [0097]) overlapping the gate electrode (460B, ⁋ [0096]) and an upper active layer (430B/431B+432B) on the first lower active layer and not overlapping the gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the two active layer patterns as taught by Kwon into the thin film transistor of Lee as the two conductive members are arranged to decrease resistance between a channel region of the oxide semiconductor layer and the source and drain electrodes (⁋ [0010]).
The combination of Lee in view of Kwon teaches wherein the first lower active layer (Kwon, Fig 4B, 420B) includes a same semiconductor material (⁋ [0054], Ga) as the second lower active layer (Lee, Fig. 6, 641, ⁋ [0154], Ga) and is disposed on a same layer as the second lower active layer, and wherein the first upper active layer (Kwon, 430B, IZO) includes a same semiconductor material (⁋ [0079], combination of In, Zn and an oxide thereof) as the second upper active layer (Lee, 643, ⁋ [0154], and is on the same layer as the second upper active layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date to apply the teaching of materials as taught by kwon, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
As to claim 3, Lee in view of Kwon teaches the thin film transistor substrate according to claim 1, Kwon teaches further comprising: a gate insulating layer (⁋ [0096], 450B, Fig. 4B) between the first gate electrode (460B) and the first active layer (420B+430B), a first contact hole included in the gate insulating layer exposing the first upper active layer (Fig. 7D, ⁋ [0117], “a first contact hole and a second contact hole are formed in at least one of the first and second insulating layers”), and wherein the first upper active layer (430B) includes a first upper conductive part in a portion exposed by the first contact hole (⁋ [0097], “a conductive layer”).
Claims 4-10, 12-13, 16-17, 20-21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kwon, and further in view of Jeong et al. (US 2021/0399142 A1), hereafter “Jeong”.
As to claim 4, Lee in view of Kwon teaches the thin film transistor substrate according to claim 3, but fails to teach further comprising:
a first connection electrode on the gate insulating layer and coupled to the first upper conductive part, wherein the first connection electrode includes a same material as the first gate electrode.
Jeong teaches a thin film transistor (⁋ [0009]) with an auxiliary electrode (Fig. 4, 320, ⁋ [0071]) on a gate insulating layer (Fig.1, 130, ⁋ [0039]) and coupled to a conductive part (122M, ⁋ [0042]) and the connection electrode has a same material (⁋ [0078]) as the gate electrode taught by Lee (671+672, ⁋ [0171]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the auxiliary electrode as taught by Jeong to the device of Lee modified by Kim to provide the electrical connection between the auxiliary electrode and the conduction part to improve the operation performance of the thin film transistor (⁋ [0110]).
As to claim 5, Lee in view of Kwon and Jeong teach he thin film transistor substrate according to claim 4, Jeong further teaches wherein at least a portion of the first connection electrode (320) is on a same layer as the first gate electrode (143, Fig. 4, ⁋ [0076]), and
wherein the first connection electrode is coupled to the first source electrode or the first drain electrode (142, Fig. 4, ⁋ [0039]).
As to claim 6, Lee in view of Kwon and Jeong teach the thin film transistor substrate according to claim 4, Lee further teaches wherein the gate insulating layer includes a first gate insulating layer (660 of Tr2, Fig. 6, ⁋ [0157]) overlapping the first gate electrode (672) a second gate insulating layer (660 of Tr1) and wherein the first gate insulating layer (660 of Tr2) and the second gate insulating layer (660 of Tr1) are spaced apart from each other. Lee doesn’t teach the second gate overlapping the first connection electrode, however, Jeong’s auxiliary electrode was incorporated to teach the first connection electrode and teaches the second gate insulating layer (130) overlapping the auxiliary electrode (320).
As to claim 7, Lee in view of Kwon teach the thin film transistor substrate according to claim 1, but fail to teach wherein the first lower active layer includes a first channel part overlapping the first gate electrode, a first connection part overlapping the first upper active layer, and a first lower conductive part disposed between the first channel part and the first connection part.
Jeong teaches a thin film transistor (⁋ [0009]) with a a semiconductor layer i.e. active layer (Fig. 1, 120, ⁋ [0041]) containing a channel portion (123, ⁋ [0041]) overlapping a gate electrode (143, ⁋ [0039]), a connection portion (122M, ⁋ [0042]), and a conductive part (122A, ⁋ [0042]) disposed between the channel and connection part.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the semiconductor layer teaching of Jeong and modify the lower active layer in the device of Lee modified by Kim to contain portions with different electrical conductivity which may be distinguished from each other (⁋⁋ [0054]-[0055]) and may be conductorized by supplied hydrogen (⁋ [0050]).
As to claim 8, Lee teaches a thin film transistor substrate A thin film transistor substrate comprising:
a substrate (Fig. 6, 610, ⁋ [0141]);
a first thin film transistor (Tr2, ⁋ [0141]) on the substrate, the first thin film transistor including a first gate electrode (⁋ [0143], 672), a first active layer (642), a first source electrode (683), and a first drain electrode (684); and
a second thin film transistor (Tr1, ⁋ [0141]) on the substrate, the second thin film transistor including a second gate electrode (671, ⁋ [0142]), a second active layer (641+643, ⁋ [0142]) with a pattern different from a pattern of the first active layer (first active layer contains 1 layer and second active layer contains 2), a second source electrode (682), and a second drain electrode (681), and
a gate insulating layer between the second gate electrode and the second active layer,
wherein the second active layer includes a second lower active layer (641) overlapping the second gate electrode (671) and a second upper active layer (643) on the second lower active layer and overlapping the second gate electrode (671),
Lee fails to teach wherein the first active layer includes a first lower active layer overlapping the first gate electrode and a first upper active layer on the first lower active layer and not overlapping the first gate electrode, wherein the gate insulating layer includes a second contact hole exposing the second upper active layer, and wherein the second upper active layer includes a second upper conductive part in a portion exposed by the second contact hole.
Kwon teaches a thin film transistor (⁋ [0096], “a thin film transistor”) with a lower active layer (Fig. 4B, 420B, ⁋ [0097]) overlapping the gate electrode (460B, ⁋ [0096]) and an upper active layer (430B/431B+432B) on the first lower active layer and not overlapping the gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the two active layer patterns as taught by Kwon into the thin film transistor of Lee as the two conductive members are arranged to decrease resistance between a channel region of the oxide semiconductor layer and the source and drain electrodes (⁋ [0010]).
Lee in view of Kwon fail to teach wherein the gate insulating layer includes a second contact hole exposing the second upper active layer, and wherein the second upper active layer includes a second upper conductive part in a portion exposed by the second contact hole.
Jeong teaches a thin film transistor (⁋ [0009]) wherein the gate insulating layer (Fig.1, 130, ⁋ [0039]) with a contact hole (CNT2, ⁋ [0044]) exposing a semiconductor layer i.e. active layer (120, ⁋ [0041]) wherein the semiconductor layer includes a conductive part (122M, ⁋ [0042]) in a portion exposed by the contact hole.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the contact hole and exposure of the conductive portion as taught by Jeong to the device of Lee modified by Kim to prevent loss of the semiconductor layer and damage to the source/drain contact portion between the main source/drain electrodes and the conductive portions ⁋⁋ [0052]-[0053]). Additionally, the source/drain electrodes may be electrically connected to the conductive portions through the contact hole (⁋ [0046]) and operate as a driving transistor in a subpixel (⁋⁋ [0095]-[0096]).
As to claim 9, Lee in view of Kwon and Jeong teach the thin film transistor substrate according to claim 8, Lee further teaches wherein the second upper active layer (643) includes a second channel part (643a, ⁋ [0164]) overlapping the second gate electrode (671), and Jeong further teaches a third upper conductive part (122A, ⁋ [0146]) between the second channel part (123) and the second upper conductive part (122M).
As to claim 10, Lee in view of Kwon and Jeong teach the thin film transistor substrate according to claim 8, Jeong teaches further comprising: a second connection electrode (Fig. 4, 320, ⁋ [0071]) on the gate insulating layer (Fig.1, 130, ⁋ [0039]) and coupled to the second upper conductive part (122M, ⁋ [0042]), wherein the second connection electrode includes a same material (⁋ [0078]) as the first gate electrode (⁋ [0171]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the auxiliary electrode as taught by Jeong to the device of Lee modified by Kwon and Jeong to provide the electrical connection between the auxiliary electrode and the conduction part to improve the operation performance of the thin film transistor (⁋ [0110]).
As to claim 12, Lee in view of Kwon and Jeong teach the thin film transistor substrate according to claim 1, Lee teaches wherein the second lower active layer (641) includes a third channel part (Fig. 6, 641a, ⁋ [0165]) in a region overlapping the second gate electrode (671).
As to claim 13, Lee in view of Kwon and Jeong teach the thin film transistor substrate according to claim 1, Jeong teaches further comprising: a first light shielding layer (1010, Fig. 10, ⁋ [0113]) coupled to the first source electrode (⁋ [0118]), disposed below the first active layer, and overlapping the first active layer (⁋ [0117]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the light shielding layer of Jeong to the device of Lee modified by Kwon and Jeong so the exposure of the channel portion to light may be prevented or at least reduced. Therefore, there may be provided with stable operation characteristics of the thin film transistor TFT (⁋ [0117]).
As to claim 16, Lee in view of Kwon and Jeong teach the thin film transistor substrate according to claim 1, Lee teaches wherein the first gate electrode (672) and the second gate electrode (671) are made of a same material on a same layer (⁋ [0171]).
Lee in view of Kwon and Jeong fail to explicitly teach wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are made of a same material on a same layer, however, Lee does teach that 681-684 are source and drain electrodes (⁋⁋ [0176], [0179]).
It would have been obvious to one having ordinary skill in the art before the effective filing date to use the same material for all 4 electrodes of Lee, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
As to claim 17, Lee teaches a thin film transistor substrate comprising:
a substrate (Fig. 6, 610, ⁋ [0141);
a first thin film transistor (Tr2, ⁋ [0141]) on the substrate, the first thin film transistor including a first gate electrode (⁋ [0143], 672), a first active layer (642), a first source electrode (683), and a first drain electrode (684); and
a second thin film transistor (Tr1, ⁋ [0141]) on the substrate, the second thin film transistor including a second gate electrode (671, ⁋ [0142]), a second active layer (641+643, ⁋ [0142]) with a pattern different from a pattern of the first active layer (first active layer contains 1 layer and second active layer contains 2), a second source electrode (682), and a second drain electrode (681), and
wherein the second active layer includes a second lower active layer (641) and a second upper active layer (643) on the second lower active layer and having a same shape as the second lower active layer (Fig. 6 shows they both have the same shape).
Lee fails to teach wherein the first active layer includes a first lower active layer and two first upper active layers disposed to be spaced apart from each other on one side and another side of the first lower active layer and, wherein the first lower active layer includes a first channel part overlapping the first gate electrode, a first connection part overlapping the first upper active layer, and a first lower conductive part disposed between the first channel part and the first connection part.
Kwon teaches a thin film transistor (⁋ [0096], “a thin film transistor”) with a lower active layer (Fig. 4B, 420B, ⁋ [0097]), and two upper active layers (430B/431B+432B) spaced apart from each other on each side of the first lower active layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the two active layer patterns as taught by Kwon into the thin film transistor of Lee as the two conductive members are arranged to decrease resistance between a channel region of the oxide semiconductor layer and the source and drain electrodes (⁋ [0010]).
Lee in view of Kwon fail to teach wherein the first lower active layer includes a first channel part overlapping the first gate electrode, a first connection part overlapping the first upper active layer, and a first lower conductive part disposed between the first channel part and the first connection part.
Jeong teaches a thin film transistor (⁋ [0009]) with a a semiconductor layer i.e. active layer (Fig. 1, 120, ⁋ [0041]) containing a channel portion (123, ⁋ [0041]) overlapping a gate electrode (143, ⁋ [0039]), a connection portion (122M, ⁋ [0042]), and a conductive part (122A, ⁋ [0042]) disposed between the channel and connection part.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the semiconductor layer teaching of Jeong and modify the lower active layer in the device of Lee modified by Kwon to contain portions with different electrical conductivity which may be distinguished from each other (⁋⁋ [0054]-[0055]) and may be conductorized by supplied hydrogen (⁋ [0050]).
As to claim 20, Lee in view of Kwon and Jeong teach the thin film transistor substrate according to claim 17, Kwon further teaches wherein the first upper active layer (430B) includes a first upper conductive part (⁋ [0097], “a conductive layer”), Lee further teaches wherein the second upper active layer (643) includes a second channel part (643a, ⁋ [0164]) overlapping the second gate electrode (671), a second upper conductive part (643b, ⁋ [0178]) on one side of the second channel part, and wherein the second lower active layer (641) includes a third channel part (641a, ⁋ [0165]) overlapping the second gate electrode (671).
Lee in view of Kwon fails to teach a third upper conductive part between the second channel part and the second upper conductive part.
Jeong teaches a thin film transistor (⁋ [0009]) with a semiconductor layer i.e. active layer (Fig. 1, 120, ⁋ [0041]) containing a channel portion (123, ⁋ [0041]), a conductorization portion (122M, ⁋ [0042]), and a sub-conductorization portion (122A, ⁋ [0042]) disposed between the channel and the conductorization portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the semiconductor layer teaching of Jeong and modify the upper active layer in the device of Lee modified by Kwon to contain portions with different electrical conductivity which may be distinguished from each other (⁋⁋ [0054]-[0055]) and may be conductorized by supplied hydrogen (⁋ [0050]).
As to claim 21, Lee in view of Kwon and Jeong teach the thin film transistor substrate according to claim 20, and further teach wherein Kwon’s first upper conductive part (432B) is in contact with Jeong’s first lower conductive part (122A).
Kwon’s incorporated first upper active layers do not overlap with the channel layer of the first lower active layers, therefore Kwon’s first upper conductive part (432B, Fig. 4B) would be in contact with Jeong’s incorporated first lower conductive part (122A, Fig. 1) which does not overlap the channel layer.
As to claim 23, Lee in view of Kwon and Jeong teach the thin film transistor substrate according to claim 20, but fail to teach a first connection electrode coupled to the first upper conductive part and a second connection electrode coupled to the second upper conductive part, wherein the first connection electrode, the second connection electrode, the first gate electrode, and the second gate electrode are made of a same material.
Jeong teaches a thin film transistor (⁋ [0009]) with a first and second auxiliary electrode (Fig. 4, 310+320, ⁋ [0071]) electrically couple to a first and second conductive part respectively (121M+122M, ⁋ [0042]) and the auxiliary electrodes have a same material (⁋ [0078]) as the gate electrodes taught by Lee (671+672, ⁋ [0171]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the auxiliary electrode as taught by Jeong to the device of Lee modified by Kim to provide the electrical connection between the auxiliary electrode and the conduction part to improve the operation performance of the thin film transistor (⁋ [0110]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kwon, Jeong and further in view of Jeon et al. (US 2020/0144309 A1), hereafter “Jeon”.
As to claim 15, Lee in view of Kwon and Jeong teach the thin film transistor substrate according to claim 13, but fails to teach a second light shielding layer disposed below the first active layer and constituting a capacitor along with the first light shielding layer.
Jeon teaches a thin film transistor (⁋ [0008]) wherein a second light shielding layer (312, Fig. 4, ⁋ [0104]) is located below an active layer (131, ⁋ [0057]) and along with another shield layer (311, ⁋ [0104]) constitutes a capacitor (⁋ [0104], “The first blocking layer 311 and the second blocking layer 312 may be disposed to overlap each other to form a capacitor”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the second shielding layer as taught by Jeon into the device of Lee, Kwon and Jeong so that the hydrogen generated in the substrate may be suppressed from diffusing to the second active layer of the second thin film transistor (⁋ [0105]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kwon, Jeong and further in view of Park et al. (US 2018/0151606 A1), hereafter “Park”.
As to claim 18, Lee in view of Kwon and Jeong teach wherein the first lower active layer and the second lower active layer include a same semiconductor material (Jeong teaches layer 120 of Fig. 1 as an oxide semiconductor layer Par. 41; Lee teaches layer 641 of Fig. 6 as an oxide semiconductor Par. 154), wherein the first upper active layer and the second upper active layer include a same semiconductor material (Kwon teaches layer 430B of Fig. 4B as a indium zinc oxide (IZO) Par. 79, 98; Lee teaches layer 643 as zinc-indium oxide (ZIO) Par. 156), however, fails to teach wherein a carrier mobility of each of the first upper active layer and the second upper active layer is greater than a carrier mobility of each of the first lower active layer and the second lower active layer.
Park teaches a thin film transistor wherein with a channel layer i.e. lower active layer consisting of an oxide semiconductor wherein the oxide semiconductor may be IGZO (InGaZnO) consisting of indium (In), gallium (Ga), zinc (Zn), and oxygen (O) (Par. 152).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of an active layer formed of an oxide semiconductor taught by Park into the lower active layers of Lee in view of Kwon and Jeong because it would’ve already been in the purview of one skilled in the art that an oxide semiconductor material can be made of IGZO.
As a result, the modification of Lee in view of Kwon, Jeong by Park teach the limitations wherein a carrier mobility of each of the first upper active layer (IZO) and the second upper active layer (IZO) is greater than a carrier mobility of each of the first lower active layer (IGZO) and the second lower active layer (IGZO) (the materials are the same as the upper and lower active layers of the instant application Par. 64-65, 103-104).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kwon, Jeong, Park and further in view of Huang (US 2023/0187484 A1), hereafter “Huang”.
As to claim 19, Lee in view of Kwon, Jeong and Park teach the thin film transistor substrate according to claim 18,
wherein the first upper active layer and the second upper active layer include at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IZO(InZnO)-based oxide semiconductor material, an IGZTO(InGaZnSnO)-based oxide semiconductor material, an ITZO(InSnO)-based oxide semiconductor material, a FIZO(FeInZnO)-based oxide semiconductor material, a ZnO-based semiconductor material, a SIZO(SiInZnO)-based oxide semiconductor material, and a ZnON(Zn-Oxynitride)-based oxide semiconductor material (see claim 18),
wherein the first lower active layer and the second lower active layer include at least one of an IGZO(InGaZnO)-based oxide semiconductor material, a GZO(GaZnO)-based oxide semiconductor material, an IGO(InGaZnO)-based oxide semiconductor material, and a GZTO(GaZnSnO)-based oxide semiconductor material (see claim 18), and
when the first lower active layer, and the second lower active layer are made of IGZO(InGaZnO)-based oxide semiconductor materials (see claim 18).
Lee in view of Kwon, Jeong and Park fail to teach when the first upper active layer, and the second upper active layer are made of IGZO(InGaZnO)-based oxide semiconductor materials, a concentration of indium (In) of the first and second upper active layers is greater than a concentration of indium (In) of the first and second lower active layers.
Huang teaches a thin film transistor (⁋ [0003]) with a lower active layer (122, Fig. 5, ⁋ [0034]) and upper active layer (124) made of IGZO (⁋ [0021], 120 is a combination of 122+124) wherein the indium concentration of the lower active layer is lower than the indium concentration of the upper active layer (⁋ [0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the upper active layers material and indium concentrations of Huang into the device of Lee in view of Kwon, Jeong and Park so hot-carrier effects generated by the lateral electric field between both channel regions and doped regions may be further alleviated, so as to improve reliability of the semiconductor device (⁋ [0045]).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kwon, Jeong and further in view of Kim et al. (US 2023/0320136 A1), hereafter “Kim”.
As to claim 22, Lee in view of Kwon and Jeong teach the thin film transistor substrate according to claim 20, and Kwon further teaches a first upper active layer including a first upper conductive part (430B) and Lee further teaches a second upper active layer including a second upper conductive part (643b), but they fail to explicitly teach wherein the first upper active layer further includes a first upper non-conductive part coupled to the first upper conductive part, and wherein the second upper active layer further includes a second upper non-conductive part coupled to the second upper conductive part.
Kim teaches a thin film transistor wherein a portion of the semiconductor layer has a non-conductive second portion couple to a conductive first portion (⁋ [0097], Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date incorporate the teaching of the non-conductive portion of Kim into the device of Lee in view of Kwon and Jeong because the second portion is not exposed to a plasma treatment and thus does not become conductive, the portions thereof may have different properties from those of portions exposed to the plasma treatment (⁋ [0096]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARNELL HUNTER whose telephone number is (571)270-1796. The examiner can normally be reached Monday - Friday 7:30 am - 4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights