DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 03/05/2026.
Applicant’s amendments filed 03/05/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1, 3, 9, 11, 13, and 18.
Claim Objections
Claims 3 and 13 are objected to because of the following informalities:
Claim 3 recites “the recess” (lines 4 and 6-7) which should be replaced with “the first recess”, to avoid antecedent basis issue.
Claim 13 recites “the recess” (line 6) which should be replaced with “the first recess”, to avoid antecedent basis issue.
Appropriate correction is required.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/05/2026 was filed after the mailing date of the Non-Final Office Action on 12/05/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9-11, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over ”A review of selective area grown recess structure for insulated-gate E-mode GaN transistors”, Japanese Journal of Appl. Phys. 59 (2020) (SA0806, pp.1-12) to He et al. (hereinafter He) in view of Oka (US 2014/0004669), Tsuchiya et al. (US Patent No. 10,084,052, hereinafter Tsuchiya), and Mishra et al. (US 2009/0267078, hereinafter Mishra).
With respect to claim 1, He discloses a method (e.g., forming selective area grown recess structure for MIS-HFET GaN transistor) (He, Figs. 1-3, Abstract, pp.1-12), comprising:
depositing, with a first epitaxial growth process (e.g., metal organic chemical vapor deposition (MOCVD)) (He, Fig. 1(1), p.SA0806-1, Col. 2, section 2, initial process for SAG (selective area growth) recess structure), a GaN layer (e.g., i-GaN layer) of a high electron mobility transistor (HEMT);
depositing, on the GaN layer, a passivation layer (e.g., SiO2 mask) (He, Fig. 1(2), p.SA0806-1, Col. 2);
forming, on the GaN layer, a passivation remnant by patterning the passivation layer (He, Fig. 1(3), p.SA0806-1, Col. 2; p.SA0806-2, Cols. 1-2);
depositing, on the GaN layer, a channel layer (SAG-GaN layer) (He, Figs. 1(4), 3(c), p.SA0806-1, Col. 2; p.SA0806-3, Cols. 1-2) and a barrier layer (SAG-AlGaN layer) of the HEMT by performing a second epitaxial growth process (e.g., regrowth by MOCVD) in the presence of the passivation remnant;
forming a first recess (He, Figs. 1(5), 3(c), p.SA0806-1) in the channel layer by removing the passivation remnant;
forming a gate electrode (He, Figs. 1(5), 3(c), 10, p.SA0806-6) of the HEMT in the first recess.
Further, He does not specifically disclose (1) depositing, with a first epitaxial growth process, a back barrier layer; (2) forming a second recess in the channel layer after forming the gate electrode, wherein the first recess is deeper than the second recess; and forming a source electrode in the second recess.
Regarding (1), Oka teaches a method of forming HEMT device (Oka, Figs. 1, 2A-2D, 8, ¶0078-¶0106, ¶0122-¶0127) that comprises depositing, with a first epitaxial growth process (e.g., MOCVD process), a back barrier layer (e.g., 750) (Oka, Fig. 8, ¶0122-¶0127), wherein the back barrier layer (e.g., 750) is formed before forming a silicon oxide mask (113) (Oka, Figs. 2B, 8, ¶0101-¶0103, ¶0122-¶0127), to provide a barrier for electrons such that a current path is blocked via a region away from the heterojunction interface between the channel layer (104) and the second barrier layer (105) to reduce leakage current between the source electrode and the drain electrode (Oka, Figs. 2A-2D, 8, ¶0123-¶0126).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He by forming a back barrier layer in the MOCVD growth chamber before forming silicon oxide mask as taught by Oka to have the method, comprising: depositing, with a first epitaxial growth process, a back barrier layer, in order to provide a barrier for electrons such that a current path is blocked via a region away from the heterojunction interface between the channel layer and the second barrier layer to reduce leakage current between the source electrode and the drain electrode (Oka, ¶0123-¶0126).
Regarding (2), Tsuchiya teaches forming AlGaN/GaN HEMT (Tsuchiya, Figs. 1, 7A-7D, Col. 2, lines 10-13; Col. 5, lines 40-67; Col. 6, 1-67; Cols. 7-9) that functions as normally-off switching device comprising forming a second recess (e.g., trench portions 3b/3c for the source/drain electrodes 6/7) (Tsuchiya, Figs. 1, 7D, Col. 10, lines 24-50) after forming the gate electrode (5), wherein the first recess (3a) is deeper than the second recess (3b/3c); and forming a source electrode (6) in the second recess (3b), to provide a switching device with improved performance characteristics and longtime reliability (Tsuchiya, Col. 2, lines 10-13; Col. 6, lines 37-43; lines 59-65; Col. 10, lines 8-50).
Further, Mishra teaches forming a switching device (Mishra, Figs. 13A-13B, 18A-18B, ¶0006, ¶0074, ¶0076-¶0078, ¶0088) having reduced on-resistance by forming the source electrode (93) and drain electrode (99) extending to the channel layer (95) including 2DEG region and having two channel access regions connected to the source electrode (93) and the drain electrode (99), wherein the first recess for the gate electrode (91) is deeper than the second recess for the source/drain electrode (93/99).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He by forming the source electrode in the source trench after forming the gate electrode as taught by Tsuchiya, wherein the source electrode extends into the channel layer as taught by Mishra to have the method, comprising: forming a second recess in the channel layer after forming the gate electrode, wherein the first recess is deeper than the second recess; and forming a source electrode in the second recess, in order to provide a switching device with improved performance characteristics and longtime reliability; and to reduce on-resistance of the switching device by connecting the source/drain electrode to the channel access region (Tsuchiya, Col. 2, lines 10-13; Col. 6, lines 37-43; lines 59-65; Col. 10, lines 8-506; Mishra, ¶0006, ¶0074, ¶0076-¶0078, ¶0088).
Regarding claim 9, He in view of Oka, Tsuchiya, and Mishra discloses the method of claim 1. Further, He discloses the method, comprising forming the source electrode (He, Fig. 10, p.SA0806-6) of the HEMT and a drain electrode of the HEMT in contact (e.g., the limitation “in contact” does not require two elements to be in direct contact) with the channel layer (SAG-GaN).
Regarding claim 10, He in view of Oka, Tsuchiya, and Mishra discloses the method of claim 9. Further, He discloses the method, wherein the drain electrode is farther from the gate electrode than is the source electrode (e.g., Lgs=4 mm and Lgd= 5 mm) (He, Figs. 10-11, p.SA0806-6 and SA0806-7).
With respect to claim 11, He discloses a method (e.g., forming selective area grown recess structure for MIS-HFET GaN transistor) (He, Figs. 1-3, Abstract, pp.1-12), comprising:
depositing, with a first epitaxial growth process (e.g., metal organic chemical vapor deposition (MOCVD)) (He, Fig. 1(1), p.SA0806-1, Col. 2, section 2, initial process for SAG (selective area growth) recess structure), a GaN buffer layer of a high electron mobility transistor (HEMT);
depositing, with the first epitaxial growth process (e.g., MOCVD), a first portion of a channel layer (e.g., i-GaN) (He, Fig. 1(1), p.SA0806-1) of the HEMT on the GaN buffer layer;
depositing, on the first portion of the channel layer (e.g., i-GaN layer), a passivation layer (e.g., SiO2 mask) (He, Fig. 1(2), p.SA0806-1, Col. 2);
forming, on the first portion of the channel layer (e.g., i-GaN layer), a passivation remnant by patterning the passivation layer (He, Fig. 1(3), p.SA0806-1, Col. 2; p.SA0806-2, Cols. 1-2);
depositing, on the first portion of the channel layer (e.g., i-GaN layer), a second portion of the channel layer (SAG-GaN layer) (He, Figs. 1(4), 3(c), p.SA0806-1, Col. 2; p.SA0806-3, Cols. 1-2) and a barrier layer (SAG-AlGaN layer) of the HEMT by performing a second epitaxial growth process (e.g., regrowth by MOCVD) in the presence of the passivation remnant;
forming a first recess in the channel layer by removing the passivation remnant (e.g., forming a recess) (He, Figs. 1(5), 3(c), p.SA0806-1);
forming a gate electrode (He, Figs. 1(5), 3(c), 10, p.SA0806-6) of the HEMT in the recess.
Further, He does not specifically disclose (1) depositing, with a first epitaxial growth process, a back barrier layer; depositing, with the first epitaxial growth process, a first portion of a channel layer on the back barrier layer; (2) forming a second recess in the channel layer after forming the gate electrode, wherein the first recess is deeper than the second recess; and forming a source electrode in the second recess.
Regarding (1), Oka teaches a method of forming HEMT device (Oka, Figs. 1, 2A-2D, 8, ¶0078-¶0106, ¶0122-¶0127) that comprises depositing, with a first epitaxial growth process (e.g., MOCVD process), a back barrier layer (e.g., 750) (Oka, Fig. 8, ¶0122-¶0127) between the buffer layer (102) and a first portion of the channel layer (103), wherein the back barrier layer (e.g., 750) is formed before forming a silicon oxide mask (113) (Oka, Figs. 2B, 8, ¶0101-¶0103, ¶0122-¶0127), to provide a barrier for electrons such that a current path is blocked via a region away from the heterojunction interface between the channel layer (104) and the second barrier layer (105) to reduce leakage current between the source electrode and the drain electrode (Oka, Figs. 2A-2D, 8, ¶0123-¶0126).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He by forming a back barrier layer in the MOCVD growth chamber before forming silicon oxide mask and between the buffer layer and the first portion of the channel layer as taught by Oka to have the method, comprising: depositing, with a first epitaxial growth process, a back barrier layer; depositing, with the first epitaxial growth process, a first portion of a channel layer on the back barrier layer, in order to provide a barrier for electrons such that a current path is blocked via a region away from the heterojunction interface between the channel layer and the second barrier layer to reduce leakage current between the source electrode and the drain electrode (Oka, ¶0123-¶0126).
Regarding (2), Tsuchiya teaches forming AlGaN/GaN HEMT (Tsuchiya, Figs. 1, 7A-7D, Col. 2, lines 10-13; Col. 5, lines 40-67; Col. 6, 1-67; Cols. 7-9) that functions as normally-off switching device comprising forming a second recess (e.g., trench portions 3b/3c for the source/drain electrodes 6/7) (Tsuchiya, Figs. 1, 7D, Col. 10, lines 24-50) after forming the gate electrode (5), wherein the first recess (3a) is deeper than the second recess (3b/3c); and forming a source electrode (6) in the second recess (3b), to provide a switching device with improved performance characteristics and longtime reliability (Tsuchiya, Col. 2, lines 10-13; Col. 6, lines 37-43; lines 59-65; Col. 10, lines 8-50).
Further, Mishra teaches forming a switching device (Mishra, Figs. 13A-13B, 18A-18B, ¶0006, ¶0074, ¶0076-¶0078, ¶0088) having reduced on-resistance by forming the source electrode (93) and drain electrode (99) extending to the channel layer (95) including 2DEG region and having two channel access regions connected to the source electrode (93) and the drain electrode (99), wherein the first recess for the gate electrode (91) is deeper than the second recess for the source/drain electrode (93/99).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He by forming the source electrode in the source trench after forming the gate electrode as taught by Tsuchiya, wherein the source electrode extends into the channel layer as taught by Mishra to have the method, comprising: forming a second recess in the channel layer after forming the gate electrode, wherein the first recess is deeper than the second recess; and forming a source electrode in the second recess, in order to provide a switching device with improved performance characteristics and longtime reliability; and to reduce on-resistance of the switching device by connecting the source/drain electrode to the channel access region (Tsuchiya, Col. 2, lines 10-13; Col. 6, lines 37-43; lines 59-65; Col. 10, lines 8-506; Mishra, ¶0006, ¶0074, ¶0076-¶0078, ¶0088).
Regarding claim 14, He in view of Oka, Tsuchiya, and Mishra discloses the method of claim 11. Further, He discloses the method, wherein removing the passivation remnant includes performing a wet etch (e.g., buffered oxide etch (BOE)) (He, Figs. 1(5),3(c), p.SA0806-1,Col. 2).
Regarding claim 15, He in view of Oka, Tsuchiya, and Mishra discloses the method of claim 11. Further, He discloses the method, wherein the first portion of the channel layer (e.g., i-GaN) and the second portion of the channel layer (SAG-GaN, as in Fig. 3(c)) are gallium nitride (He, Figs. 1(4), 3(c), p.SA0806-1, p.SA0806-3).
Regarding claim 16, He in view of Oka, Tsuchiya, and Mishra discloses the method of claim 11. Further, He discloses the method, wherein the first portion of the channel layer includes intrinsic gallium nitride (e.g., i-GaN), but does not specifically disclose that the second portion of the channel layer includes intrinsic gallium nitride.
However, He teaches forming the second portion of the channel layer (e.g., SAG-GaN) (He, Figs. 1(4), 3(c), p.SA0806-1, pp. SA0806-3/ SA0806-4) with suppressed n-type doping to provide improved mobility of the 2DEG at the regrown heterostructure (SAG-GaN/SAG-AlGaN).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He/Oka/Tsuchiya/Mishra by suppressing n-type doping of the regrown SAG-GaN channel layer as taught by He to have the method, wherein the second portion of the channel layer includes intrinsic gallium nitride, in order to provide improved mobility of the 2DEG at the regrown heterostructure (He, pp. SA0806-3/ SA0806-4).
Regarding claim 17, He in view of Oka, Tsuchiya, and Mishra discloses the method of claim 11. Further, He discloses the method, comprising forming a source electrode (He, Fig. 10, p.SA0806-6) of the HEMT and a drain electrode of the HEMT in contact (e.g., the limitation “in contact” does not require two elements to be in direct contact) with the channel layer (SAG-GaN).
Claims 2-3 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over ”A review of selective area grown recess structure for insulated-gate E-mode GaN transistors”, Japanese Journal of Appl. Phys. 59 (2020) (SA0806, pp.1-12) to He in view of Oka (US 2014/0004669), Tsuchiya (US Patent No. 10,084,052), and Mishra (US 2009/0267078) as applied to claim 1, and further in view of Morvan (US 2017/0229567).
Regarding claim 2, He in view of Oka, Tsuchiya, and Mishra discloses the method of claim 1. Further, He does not specifically disclose the method, comprising depositing a dielectric cap layer on the barrier layer before removing the passivation remnant.
However, Oka teaches forming a barrier layer (105) (Oka, Figs. 1, 2D, ¶0087, ¶0103) having a cap layer thereon before removing the passivation remnant (e.g., mask 113), to provide HEMT device having a normally-off characteristic and low on-state resistance (Oka, Figs. 1, 2D, ¶0105).
Further, Morvan teaches forming a method of forming a high electron mobility device of normally-off type (Morvan, Fig. 1, ¶0001, ¶0025-¶0117), wherein the dielectric cap layer (20) (Morvan, Fig. 1, ¶0027, ¶0028) including silicon nitride is deposited in situ in the frame used for the epitaxy steps on the AlGaN barrier layer (17) abutting the gate structure (3) formed in a recess, to have a SiN/AlGaN interface and the cap SiN layer of a very good quality to protect the barrier layer, and to ensure an electron gas conduction and operation of accumulation field-effect transistor type in the channel (Morvan, Fig. 1, ¶0028, ¶0033).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He/Oka/Tsuchiya/Mishra by forming the cap layer before removing the mask as taught by Oka, wherein the cap layer includes a dielectric SiN layer forming SiN/AlGaN interface with the barrier layer as taught by Morvan, to have the method, comprising depositing a dielectric cap layer on the barrier layer before removing the passivation remnant, in order to provide HEMT device having a normally-off characteristic and low on-state resistance; and to provide a cap layer having a very good quality to protect the barrier layer, and to ensure an electron gas conduction and operation of accumulation field-effect transistor type in the channel (Oka, ¶0087, ¶0105; Morvan, ¶0028, ¶0033).
Regarding claim 3, He in view of Oka, Tsuchiya, Mishra, and Morvan discloses the method of claim 2. Further, He discloses the method, wherein forming the gate electrode includes: depositing a gate dielectric layer (e.g., Al2O3) (He, Fig. 10, p. SA0806-6) on sidewalls of the channel layer (SAG-GaN) and the barrier (SAG-AlGaN) in the recess, but does not specifically disclose depositing a gate dielectric layer on a top surface of the dielectric cap layer; patterning the gate dielectric layer; and filling the first recess by depositing a gate metal on the gate dielectric layer in the recess.
However, Oka teaches depositing a gate dielectric layer (108) (Oka, Fig. 1, ¶0087, ¶0104) on a top surface of the barrier layer (105) including a cap layer thereon; patterning the gate dielectric layer (e.g., forming openings in the gate dielectric layer 108 for the source electrode and the drain electrode); and filling the recess by depositing a gate metal (109) on the liner layer (e.g., portions of the gate insulating layer 108 on recess sidewalls) in the recess, to provide HEMT device having normally-off characteristics and low on-state resistance (Oka, Fig. 1, ¶0104-¶0105).
Further, Morvan teaches depositing a gate dielectric layer (e.g., Al2O3 layer 32) (Morvan, Fig. 1, ¶0028, ¶0031-¶0033) on a top surface of the dielectric cap layer (20); and filling the recess by depositing a gate metal (31) on the liner layer (e.g., Al2O3 layer 32 that lines the sidewalls of the recess) in the recess, to provide a high electron mobility device of normally-off type.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He/Oka/Tsuchiya/Mishra/Morvan by forming the gate structure in the recess and on the cap layer as taught by Oka, wherein the cap layer includes a dielectric SiN layer forming SiN/AlGaN interface with the barrier layer as taught by Morvan, to have the method, comprising depositing a gate dielectric layer on a top surface of the dielectric cap layer; patterning the gate dielectric layer; and filling the first recess by depositing a gate metal on the gate dielectric layer in the recess, in order to provide HEMT device having a normally-off characteristic and low on-state resistance; and to provide a cap layer having a very good quality to protect the barrier layer, and to ensure an electron gas conduction and operation of accumulation field-effect transistor type in the channel (Oka, ¶0087, ¶0105; Morvan, ¶0028, ¶0033).
Regarding claim 12, He in view of Oka, Tsuchiya, and Mishra discloses the method of claim 11. Further, He does not specifically disclose the method, comprising depositing a dielectric cap layer on the barrier layer before removing the passivation remnant.
However, Oka teaches forming a barrier layer (105) (Oka, Figs. 1, 2D, ¶0087, ¶0103) having a cap layer thereon before removing the passivation remnant (e.g., mask 113), to provide HEMT device having a normally-off characteristic and low on-state resistance (Oka, Figs. 1, 2D, ¶0105).
Further, Morvan teaches forming a method of forming a high electron mobility device of normally-off type (Morvan, Fig. 1, ¶0001, ¶0025-¶0117), wherein the dielectric cap layer (20) (Morvan, Fig. 1, ¶0027, ¶0028) including silicon nitride is deposited in situ in the frame used for the epitaxy steps on the AlGaN barrier layer (17) abutting the gate structure (3) formed in a recess, to have a SiN/AlGaN interface and the cap SiN layer of a very good quality to protect the barrier layer, and to ensure an electron gas conduction and operation of accumulation field-effect transistor type in the channel (Morvan, Fig. 1, ¶0028, ¶0033).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He/Oka/Tsuchiya/Mishra by forming the cap layer before removing the mask as taught by Oka, wherein the cap layer includes a dielectric SiN layer forming SiN/AlGaN interface with the barrier layer as taught by Morvan, to have the method, comprising depositing a dielectric cap layer on the barrier layer before removing the passivation remnant, in order to provide HEMT device having a normally-off characteristic and low on-state resistance; and to provide a cap layer having a very good quality to protect the barrier layer, and to ensure an electron gas conduction and operation of accumulation field-effect transistor type in the channel (Oka, ¶0087, ¶0105; Morvan, ¶0028, ¶0033).
Regarding claim 13, He in view of Oka, Tsuchiya, Mishra, and Morvan discloses the method of claim 12. Further, He discloses the method, wherein forming the gate electrode includes: depositing a gate dielectric layer (e.g., Al2O3) (He, Fig. 10, p. SA0806-6) on sidewalls of the channel layer (SAG-GaN) and the barrier (SAG-AlGaN) in the first recess, but does not specifically disclose depositing a gate dielectric layer on a top surface of the dielectric cap layer; patterning the gate dielectric layer; and filling the first recess by depositing a gate metal on the gate dielectric layer in the recess.
However, Oka teaches depositing a gate dielectric layer (108) (Oka, Fig. 1, ¶0087, ¶0104) on a top surface of the barrier layer (105) including a cap layer thereon; patterning the gate dielectric layer (e.g., forming openings in the gate dielectric layer 108 for the source electrode and the drain electrode); and filling the recess by depositing a gate metal (109) on the gate dielectric layer (e.g., portions of the gate insulating layer 108 on recess sidewalls) in the recess, to provide HEMT device having normally-off characteristics and low on-state resistance (Oka, Fig. 1, ¶0104-¶0105).
Further, Morvan teaches depositing a gate dielectric layer (e.g., Al2O3 layer 32) (Morvan, Fig. 1, ¶0028, ¶0031-¶0033) on a top surface of the dielectric cap layer (20); and filling the recess by depositing a gate metal (31) on the gate dielectric layer (e.g., Al2O3 layer 32 that lines the sidewalls of the recess) in the recess, to provide a high electron mobility device of normally-off type.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He/Oka/Tsuchiya/Mishra/Morvan by forming the gate structure in the recess and on the cap layer as taught by Oka, wherein the cap layer includes a dielectric SiN layer forming SiN/AlGaN interface with the barrier layer as taught by Morvan, to have the method, comprising depositing a gate dielectric layer on a top surface of the dielectric cap layer; patterning the gate dielectric layer; and filling the first recess by depositing a gate metal on the gate dielectric layer in the recess, in order to provide HEMT device having a normally-off characteristic and low on-state resistance; and to provide a cap layer having a very good quality to protect the barrier layer, and to ensure an electron gas conduction and operation of accumulation field-effect transistor type in the channel (Oka, ¶0087, ¶0105; Morvan, ¶0028, ¶0033).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over ”A review of selective area grown recess structure for insulated-gate E-mode GaN transistors”, Japanese Journal of Appl. Phys. 59 (2020) (SA0806, pp.1-12) to He in view of Oka (US 2014/0004669), Tsuchiya (US Patent No. 10,084,052), and Mishra (US 2009/0267078) as applied to claim 1, and further in view of Yang et al. (US 2019/0103482, hereinafter Yang).
Regarding claim 4, He in view of Oka, Tsuchiya, and Mishra discloses the method of claim 1. Further, He does not specifically disclose the method, wherein the first epitaxial growth process forms an aluminum nitride layer on a semiconductor substrate, a super lattice on the aluminum nitride layer, a first layer of gallium nitride doped with carbon on the super lattice, and the back barrier layer on the first layer of gallium nitride.
However, Yang teaches a method of forming a recess E-mode GaN power device (Yang, Fig. 3, ¶0019-¶0037), wherein the first epitaxial growth process (e.g., MOCVD) (Yang, Fig. 3, ¶0027) forms an aluminum nitride layer (e.g., AlN nucleation layer 1011/1012) (Yang, Fig. 3, ¶0030-¶0032) on a semiconductor substrate (100) (Yang, Fig. 3, ¶0029), a super lattice (e.g., strain structure 1021 including a superlattice structure AlmGa1-mN/AlnGa1-nN) (Yang, Fig. 3, ¶0033-¶0034) on the aluminum nitride layer (1011/1021), a first layer of gallium nitride doped with carbon (1022) (Yang, Fig. 3, ¶0035-¶0036) on the super lattice (1021), and the back barrier layer (103) (Yang, Fig. 3, ¶0028, ¶0039-¶0044) on the first layer of gallium nitride (1022). In Yang, the nucleation layer (101) is provided to reduce the growth stress of the overlying nitride layers on the substrate, and the gallium nitride doped with carbon is designed to block the leakage current in the buffer structure (102) or the substrate (100), and the back barrier layer is configured to reduce the current collapse effect (Yang, Fig. 3, ¶0024, ¶0037, ¶0039-¶0043).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He/Oka/Tsuchiya/Mishra by forming the nucleation layer, the strain structure, and the back-barrier layer on a substrate as taught by Yang to have the method, wherein the first epitaxial growth process forms an aluminum nitride layer on a semiconductor substrate, a super lattice on the aluminum nitride layer, a first layer of gallium nitride doped with carbon on the super lattice, and the back barrier layer on the first layer of gallium nitride, in order to reduce the growth stress of the overlying nitride layers on the substrate, to block the leakage current in the buffer structure or the substrate, and to reduce the current collapse effect (Yang, ¶0024, ¶0037, ¶0039-¶0043).
Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over ”A review of selective area grown recess structure for insulated-gate E-mode GaN transistors”, Japanese Journal of Appl. Phys. 59 (2020) (SA0806, pp.1-12) to He in view of Oka (US 2014/0004669), Tsuchiya (US Patent No. 10,084,052), and Mishra (US 2009/0267078) as applied to claim 1, and further in view of Morvan (US 2017/0229567) and Yang (US 2019/0103482).
Regarding claim 4, He in view of Oka, Tsuchiya, and Mishra discloses the method of claim 1. Further, He does not specifically disclose the method, wherein the first epitaxial growth process forms an aluminum nitride layer on a semiconductor substrate, a super lattice on the aluminum nitride layer, a first layer of gallium nitride doped with carbon on the super lattice, and the back barrier layer on the first layer of gallium nitride.
However, Morvan teaches a method of forming a high electron mobility device of normally-off type (Morvan, Fig. 1, ¶0001, ¶0025-¶0117), wherein the first epitaxial growth process forms an aluminum nitride layer (e.g., AlN nucleation layer 12) (Morvan, Fig. 1, ¶0025, ¶0039) on a semiconductor substrate (11) (Yang, Fig. 3, ¶0038), a first layer of gallium nitride doped with carbon (13) (Morvan, Fig. 1, ¶0040), and the back barrier layer (e.g., P-doped GaN layer 14) (Morvan, Fig. 1, ¶0041, ¶0043, ¶0104-¶0106) on the first layer of gallium nitride (13). In Morvan, the nucleation layer (12) is provided to reduce the mismatch of parameters (e.g., CTEs, coefficients of thermal expansion) between the overlying nitride layers on the substrate, and the gallium nitride doped with carbon is designed to block the leakage current, and the back barrier layer is configured to obtain a complete depletion of the back barrier layer, and to improve electrical characteristics of the electron gas layer (18) (Morvan, Fig. 1, ¶0026, ¶0039, ¶0043, ¶0116).
Further, Yang teaches a method of forming a recess E-mode GaN power device (Yang, Fig. 3, ¶0019-¶0037), wherein the first epitaxial growth process (e.g., MOCVD) (Yang, Fig. 3, ¶0027) forms an aluminum nitride layer (e.g., AlN nucleation layer 1011/1012) (Yang, Fig. 3, ¶0030-¶0032) on a semiconductor substrate (100) (Yang, Fig. 3, ¶0029), a super lattice (e.g., strain structure 1021 including a superlattice structure AlmGa1-mN/AlnGa1-nN) (Yang, Fig. 3, ¶0033-¶0034) on the aluminum nitride layer (1011/1021), a first layer of gallium nitride doped with carbon (1022) (Yang, Fig. 3, ¶0035-¶0036) on the super lattice (1021), and the back barrier layer (103) (Yang, Fig. 3, ¶0028, ¶0039-¶0044) on the first layer of gallium nitride (1022). In Yang, the nucleation layer (101) is provided to reduce the growth stress of the overlying nitride layers on the substrate, and the gallium nitride doped with carbon is designed to block the leakage current in the buffer structure (102) or the substrate (100), and the back barrier layer is configured to reduce the current collapse effect (Yang, Fig. 3, ¶0024, ¶0037, ¶0039-¶0043).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He/Oka/Tsuchiya/Mishra by forming the nucleation layer and the back-barrier layer on a substrate as taught by Morvan, wherein the strain structure including superlattice is formed between the nucleation layer and the back-barrier layer as taught by Yang to have the method, wherein the first epitaxial growth process forms an aluminum nitride layer on a semiconductor substrate, a super lattice on the aluminum nitride layer, a first layer of gallium nitride doped with carbon on the super lattice, and the back barrier layer on the first layer of gallium nitride, in order to reduce the mismatch of parameters (e.g., CTEs) between the overlying nitride layers on the substrate, to block the leakage current, and to improve electrical characteristics of the electron gas layer; and to block the leakage current in the buffer structure or the substrate, and to reduce the current collapse effect ((Morvan, ¶0026, ¶0039, ¶0043, ¶0116; Yang, ¶0024, ¶0037, ¶0039-¶0043).
Regarding claims 5-7, He in view of Oka, Tsuchiya, Mishra, Morvan, and Yang discloses the method of claim 4. Further, He does not specifically disclose the method, wherein the back barrier layer is a second layer of gallium nitride (as claimed in claim 5); wherein the back barrier layer is doped with magnesium (as claimed in claim 6); wherein the channel layer is a third layer of gallium nitride (as claimed in claim 7).
However, Morvan teaches the method, wherein the back barrier layer (e.g., P-doped GaN layer 14) (Morvan, Fig. 1, ¶0041, ¶0043, ¶0104-¶0106) is formed on a first carbon-doped GaN layer (13) and is a second layer of gallium nitride; wherein the back barrier layer (e.g., P-doped GaN layer 14) is doped with magnesium (Morvan, Fig. 1, ¶0043); and wherein the channel layer (e.g., GaN layer 16) is a third layer of gallium nitride.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He/Oka/Tsuchiya/Mishra/Morvan/Yang by forming the P-doped GaN back-barrier layer on the first carbon-doped GaN layer as taught by Morvan to have the method, wherein the back barrier layer is a second layer of gallium nitride (as claimed in claim 5); wherein the back barrier layer is doped with magnesium (as claimed in claim 6); wherein the channel layer is a third layer of gallium nitride (as claimed in claim 7), in order to block the leakage current and to improve electrical characteristics of the electron gas layer (Morvan, ¶0025-¶0026, ¶0043, ¶0116).
Regarding claim 8, He in view of Oka, Tsuchiya, Mishra, Morvan, and Yang discloses the method of claim 7. Further, He discloses the method, wherein the barrier layer (SAG-AlGaN layer) (He, Figs. 1(4), 3(c), p.SA0806-1, Col. 2; p.SA0806-3, Cols. 1-2) is aluminum gallium nitride.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over CN106206297 to Liu et al. (hereinafter Liu) in view of Tsuchiya (US Patent No. 10,084,052) and Mishra (US 2009/0267078).
With respect to claim 18, Liu discloses a method (e.g., forming AlGaN/GaN HFET by using selective area growth (SAG) technique) (Liu, Figs. 1-8, Abstract, pp.1-5), comprising:
forming, in a first epitaxial growth process (e.g., metal organic chemical vapor deposition or molecular beam epitaxy) (Liu, Fig. 3, p. 3, Example 1), a layer of gallium nitride (e.g., growing GaN channel layer 3);
forming a dielectric structure (e.g., patterned SiO2 mask 7) (Liu, Figs. 4-5, p. 3) on the layer of gallium nitride (e.g., GaN channel layer 3);
forming, in a second epitaxial growth process (e.g., selective epitaxy by metal organic chemical vapor deposition or molecular beam epitaxy) after forming the dielectric structure (e.g., patterned SiO2 mask 7), a channel layer (e.g., GaN channel layer 4) (Liu, Fig. 6, p. 4) of a high electron mobility transistor (HEMT) on the layer of gallium nitride (e.g., GaN layer 3) in the presence of the dielectric structure (7), wherein sidewalls of the channel layer (e.g., GaN channel layer 4) abut the dielectric structure (e.g., patterned SiO2 mask 7);
forming a first recess in the channel layer by removing the dielectric structure (e.g., SiO2 mask 7) (Liu, Fig. 8, p. 4) after forming the channel layer (e.g., GaN channel layer 4);
forming a gate electrode (e.g., concave gate is formed in pace of the removed mask 7) (Liu, Fig. 8, p. 2, p. 4) of the HEMT in the first recess in place of the dielectric structure (7).
Further, Liu does not specifically disclose forming a second recess in the channel layer after forming the gate electrode, wherein the first recess is deeper than the second recess; and forming a source electrode in the second recess.
However, Tsuchiya teaches forming AlGaN/GaN HEMT (Tsuchiya, Figs. 1, 7A-7D, Col. 2, lines 10-13; Col. 5, lines 40-67; Col. 6, 1-67; Cols. 7-9) that functions as normally-off switching device comprising forming a second recess (e.g., trench portions 3b/3c for the source/drain electrodes 6/7) (Tsuchiya, Figs. 1, 7D, Col. 10, lines 24-50) after forming the gate electrode (5), wherein the first recess (3a) is deeper than the second recess (3b/3c); and forming a source electrode (6) in the second recess (3b), to provide a switching device with improved performance characteristics and longtime reliability (Tsuchiya, Col. 2, lines 10-13; Col. 6, lines 37-43; lines 59-65; Col. 10, lines 8-50).
Further, Mishra teaches forming a switching device (Mishra, Figs. 13A-13B, 18A-18B, ¶0006, ¶0074, ¶0076-¶0078, ¶0088) having reduced on-resistance by forming the source electrode (93) and drain electrode (99) extending to the channel layer (95) including 2DEG region and having two channel access regions connected to the source electrode (93) and the drain electrode (99), wherein the first recess for the gate electrode (91) is deeper than the second recess for the source/drain electrode (93/99).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Liu by forming the source electrode in the source trench after forming the gate electrode as taught by Tsuchiya, wherein the source electrode extends into the channel layer as taught by Mishra to have the method, comprising: forming a second recess in the channel layer after forming the gate electrode, wherein the first recess is deeper than the second recess; and forming a source electrode in the second recess, in order to provide a switching device with improved performance characteristics and longtime reliability; and to reduce on-resistance of the switching device by connecting the source/drain electrode to the channel access region (Tsuchiya, Col. 2, lines 10-13; Col. 6, lines 37-43; lines 59-65; Col. 10, lines 8-506; Mishra, ¶0006, ¶0074, ¶0076-¶0078, ¶0088).
Regarding claim 19, Liu in view of Tsuchiya and Mishra discloses the method of claim 18. Further, Liu discloses the method, wherein forming the dielectric structure (e.g., patterned SiO2 mask 7) (Liu, Figs. 4-5, p. 3) includes depositing a dielectric layer (e.g., SiO2 mask layer 7, as in Fig. 4) on the layer of gallium nitride (e.g., GaN layer 3) and patterning (Liu, Fig. 5, p. 3) the dielectric layer (7).
Regarding claim 20, Liu in view of Tsuchiya and Mishra discloses the method of claim 19. Further, Liu discloses the method, wherein the channel layer (e.g., GaN channel layer 4) (Liu, Fig. 6, p. 4) includes gallium nitride.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over ”A review of selective area grown recess structure for insulated-gate E-mode GaN transistors”, Japanese Journal of Appl. Phys. 59 (2020) (SA0806, pp.1-12) to He in view of Tsuchiya (US Patent No. 10,084,052) and Mishra (US 2009/0267078).
With respect to claim 18, He discloses a method (e.g., forming selective area grown recess structure for MIS-HFET GaN transistor) (He, Figs. 1-3, Abstract, pp.1-12), comprising:
forming, in a first epitaxial growth process (e.g., metal organic chemical vapor deposition (MOCVD)) (He, Fig. 1(1), p.SA0806-1, Col. 2, section 2, initial process for SAG (selective area growth) recess structure), a layer of gallium nitride (e.g., i-GaN layer);
forming a dielectric structure (e.g., patterned SiO2 mask) (He, Fig. 1(2)-1(3), p.SA0806-1, Col. 2) on the layer of gallium nitride;
forming, in a second epitaxial growth process (e.g., regrowth by MOCVD) after forming the dielectric structure (e.g., patterned SiO2 mask), a channel layer (SAG-GaN layer) (He, Figs. 1(4), 3(c), p.SA0806-1, Col. 2; p.SA0806-3, Cols. 1-2) of a high electron mobility transistor (HEMT) on the layer of gallium nitride (e.g., i-GaN layer) in the presence of the dielectric structure, wherein sidewalls of the channel layer (e.g., SAG-GaN layer, as in Fig. 3(c)) abut the dielectric structure (e.g., patterned SiO2 mask, as in Fig. 1(4));
forming a first recess in the channel layer by removing the dielectric structure (e.g., SiO2 mask) (He, Figs. 1(5), 3(c), p.SA0806-1) after forming the channel layer (e.g., SAG-GaN layer);
forming a gate electrode (He, Figs. 1(5), 3(c), 10, p.SA0806-6) of the HEMT in the first recess in place of the dielectric structure.
Further, He does not specifically disclose forming a second recess in the channel layer after forming the gate electrode, wherein the first recess is deeper than the second recess; and forming a source electrode in the second recess.
However, Tsuchiya teaches forming AlGaN/GaN HEMT (Tsuchiya, Figs. 1, 7A-7D, Col. 2, lines 10-13; Col. 5, lines 40-67; Col. 6, 1-67; Cols. 7-9) that functions as normally-off switching device comprising forming a second recess (e.g., trench portions 3b/3c for the source/drain electrodes 6/7) (Tsuchiya, Figs. 1, 7D, Col. 10, lines 24-50) after forming the gate electrode (5), wherein the first recess (3a) is deeper than the second recess (3b/3c); and forming a source electrode (6) in the second recess (3b), to provide a switching device with improved performance characteristics and longtime reliability (Tsuchiya, Col. 2, lines 10-13; Col. 6, lines 37-43; lines 59-65; Col. 10, lines 8-50).
Further, Mishra teaches forming a switching device (Mishra, Figs. 13A-13B, 18A-18B, ¶0006, ¶0074, ¶0076-¶0078, ¶0088) having reduced on-resistance by forming the source electrode (93) and drain electrode (99) extending to the channel layer (95) including 2DEG region and having two channel access regions connected to the source electrode (93) and the drain electrode (99), wherein the first recess for the gate electrode (91) is deeper than the second recess for the source/drain electrode (93/99).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of He by forming the source electrode in the source trench after forming the gate electrode as taught by Tsuchiya, wherein the source electrode extends into the channel layer as taught by Mishra to have the method, comprising: forming a second recess in the channel layer after forming the gate electrode, wherein the first recess is deeper than the second recess; and forming a source electrode in the second recess, in order to provide a switching device with improved performance characteristics and longtime reliability; and to reduce on-resistance of the switching device by connecting the source/drain electrode to the channel access region (Tsuchiya, Col. 2, lines 10-13; Col. 6, lines 37-43; lines 59-65; Col. 10, lines 8-506; Mishra, ¶0006, ¶0074, ¶0076-¶0078, ¶0088).
Regarding claim 19, He in view of Tsuchiya and Mishra in view of discloses the method of claim 18. Further, He discloses the method, wherein forming the dielectric structure (e.g., patterned SiO2 mask) (He, Figs. 1(2)-1(3), p.SA0806-1, Col. 2) includes depositing a dielectric layer (e.g., SiO2 mask layer, as in Fig. 1(2)) on the layer of gallium nitride (e.g., i-GaN) and patterning (He, Figs. 1(3), p.SA0806-1, Col. 2) the dielectric layer.
Regarding claim 20, He in view of Tsuchiya and Mishra discloses the method of claim 19. Further, He discloses the method, wherein the channel layer (e.g., SAG-GaN layer, as in Fig. 3(c)) (He, Figs. 1(4)-1(5), 3(c), p.SA0806-1, p.SA0806-3) includes gallium nitride.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0004669 to Oka in view of Tsuchiya (US Patent No. 10,084,052) and Mishra (US 2009/0267078).
With respect to claim 18, Oka discloses a method (e.g., forming high electron mobility transistor (HEMT)) (Oka, Figs. 1, 2A-2D, ¶0078-¶0106), comprising:
forming, in a first epitaxial growth process (e.g., metal organic chemical vapor deposition (MOCVD)) (Oka, Fig. 1, 2A, ¶0079, ¶0100), a layer of gallium nitride (e.g., GaN layer 103);
forming a dielectric structure (e.g., a SiO2 mask 113) (Oka, Fig. 1, 2B, ¶0079, ¶0101) on the layer of gallium nitride (103);
forming, in a second epitaxial growth process (e.g., regrowth by MOCVD) after forming the dielectric structure (e.g., the SiO2 mask 113), a channel layer (e.g., GaN layer 104) (Oka, Fig. 1, 2C, ¶0080, ¶0102) of a high electron mobility transistor (HEMT) on the layer of gallium nitride (e.g., GaN layer 103) in the presence of the dielectric structure (113), wherein sidewalls of the channel layer (e.g., 104) abut the dielectric structure (e.g., the SiO2 mask 113);
forming a first recess in the channel layer by removing the dielectric structure (e.g., the SiO2 mask) (Oka, Fig. 1, 2D, ¶0080, ¶0103) after forming the channel layer (e.g., the GaN layer 104); and
forming a gate electrode (109) (Oka, Fig. 1, 2D, ¶0080, ¶0103) of the HEMT in the first recess in place of the dielectric structure.
Further, Oka does not specifically disclose forming a second recess in the channel layer after forming the gate electrode, wherein the first recess is deeper than the second recess; and forming a source electrode in the second recess.
However, Tsuchiya teaches forming AlGaN/GaN HEMT (Tsuchiya, Figs. 1, 7A-7D, Col. 2, lines 10-13; Col. 5, lines 40-67; Col. 6, 1-67; Cols. 7-9) that functions as normally-off switching device comprising forming a second recess (e.g., trench portions 3b/3c for the source/drain electrodes 6/7) (Tsuchiya, Figs. 1, 7D, Col. 10, lines 24-50) after forming the gate electrode (5), wherein the first recess (3a) is deeper than the second recess (3b/3c); and forming a source electrode (6) in the second recess (3b), to provide a switching device with improved performance characteristics and longtime reliability (Tsuchiya, Col. 2, lines 10-13; Col. 6, lines 37-43; lines 59-65; Col. 10, lines 8-50).
Further, Mishra teaches forming a switching device (Mishra, Figs. 13A-13B, 18A-18B, ¶0006, ¶0074, ¶0076-¶0078, ¶0088) having reduced on-resistance by forming the source electrode (93) and drain electrode (99) extending to the channel layer (95) including 2DEG region and having two channel access regions connected to the source electrode (93) and the drain electrode (99), wherein the first recess for the gate electrode (91) is deeper than the second recess for the source/drain electrode (93/99).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Oka by forming the source electrode in the source trench after forming the gate electrode as taught by Tsuchiya, wherein the source electrode extends into the channel layer as taught by Mishra to have the method, comprising: forming a second recess in the channel layer after forming the gate electrode, wherein the first recess is deeper than the second recess; and forming a source electrode in the second recess, in order to provide a switching device with improved performance characteristics and longtime reliability; and to reduce on-resistance of the switching device by connecting the source/drain electrode to the channel access region (Tsuchiya, Col. 2, lines 10-13; Col. 6, lines 37-43; lines 59-65; Col. 10, lines 8-506; Mishra, ¶0006, ¶0074, ¶0076-¶0078, ¶0088).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891