DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Konishi (US 2007/0200223 A1).
With respect to claim 1, Konishi discloses, in Figs.1-18, a semiconductor device comprising: a lead frame (1, 9) including a frame main surface/(upper surface of frame 1) and a frame convex portion (8) provided on the frame main surface/(upper surface of frame 1); and a semiconductor chip (2) including a semiconductor layer (13) and an electrode (21) provided on a bottom surface of the semiconductor layer (13) and bonded to the frame convex portion (8), wherein the electrode (21) of the semiconductor chip (2) has a protrusion surrounding the frame convex portion (8), and an outer side surface of the protrusion is flush with a side surface of the semiconductor layer (13) (see Par.[0037] wherein the reference numeral 1 denotes a heatsink plate, the reference numerals 2 and 3 denote semiconductor chips, the reference numerals 4 and 5 denote adhesives, the reference numeral 6 denotes a heat generating portion, the reference numeral 7 denotes a depressed portion, the reference numeral 8 denotes a protruding potion, the reference numeral 9 denotes lead terminals, the reference numeral 10 denotes a mold resin, the reference numeral 11 denotes wires, the reference numeral 12 denotes an electrode, the reference numeral 13 denotes a wafer, the reference numeral 14 denotes a chip circuit, the reference numeral 15 denotes a mold, the reference numeral 16 denotes a base electrode, the reference numeral 17 denotes an emitter electrode, the reference numeral 18 denotes wire connecting positions, the reference numeral 19 denotes a bonding pad area, the reference numeral 20 denotes a through-hole, and the reference numeral 21 denotes a rear-face electrode).
With respect to claim 13, Konishi discloses, in Figs.1-18, the semiconductor device, wherein the semiconductor chip (2) is bonded to the lead frame via a bonding material (4).
With respect to claim 14, Konishi discloses, in Figs.1-18, the semiconductor device, wherein a thickness of the bonding material between the electrode and the frame convex portion is smaller than a height of the protrusion.
Claims 1-3 and 5-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gruenhagen et al. (US 2011/0230046 A1 hereinafter referred to as “Gruenhagen”).
With respect to claim 1, Gruenhagen discloses, in Figs.1-14, a semiconductor device comprising: a lead frame/(lead frame and its extension 240 and 245) including a frame main surface/(upper surface of 245) and a frame convex portion/(mesa portion of 245) provided on the frame main surface (see Par.[0020]-[0022] wherein semiconductor die 200 further comprises a second electrically conductive layer 245 disposed on first conductive layer 240; layer 240 may be disposed on additional portions of the die's second surface 212; layer 240 may comprise one or more metals, disposed together and/or in sub-layers; second conductive layer 245 may be maintained in an uncured or partially cured state so that a die clip, leadframe die paddle, or the like may be adhered to it, and cured after being adhered); and a semiconductor chip (220) including a semiconductor layer (220, 210) and an electrode (226, 240) provided on a bottom surface of the semiconductor layer (220, 210) and bonded to the frame convex portion, wherein the electrode (226, 240) of the semiconductor chip (220) has a protrusion surrounding the frame convex portion, and an outer side surface of the protrusion is flush with a side surface of the semiconductor layer (see Par.[0024] wherein the semiconductor device area 220 is located below drain electrodes 226; there are three mesas 233 interleaved between the two trenches 230; mesas 233 provide structural stability to semiconductor die 210 and minimize the amount of its warping from the heat generated by the device. Mesas 233 have lengths that are equal to or greater than the lengths of trenches 230, and have typical widths of 0.5 mm to 4 mm (or more); see Par.[0025] wherein second layer 245 is directly disposed on the surfaces of trenches 230, and electrode 226 of the device region 220; see Par.[0030] wherein the wafer provides the semiconductor body 210 of the die; the device regions 220 may be manufactured to provide any of the above types of power devices, including rectifiers and transistors).
With respect to claim 2, Gruenhagen discloses, in Figs.1-14, the semiconductor device, wherein the electrode (226, 240) of the semiconductor chip (2) includes, in order from the frame convex portion side, a first metal layer (226) and a second metal layer (240) laminated on the first metal layer and made of a material different from that of the first metal layer (see Par.[0019] wherein portions of source and drain electrodes 225-226 lie in the cross section and are schematically shown by respective solid lines; gate electrode 224 may comprise a conductive layer spaced from a surface of semiconductor body 210 by a dielectric layer, and electrodes 225 and 226 may comprise doped regions of semiconductor body 210 (e.g.; silicon); see Par.[0020] wherein semiconductor die 200 further comprises a first electrically conductive layer 240 disposed on trench surface 231 and a portion of the die's second surface 212 (e.g., the drain electrode 226); layer 240 may comprise one or more metals, disposed together and/or in sub-layers; copper may be used; it may have a thickness in the range of 0.5 microns to 5 microns, or more; the thickness of layer 240 is preferably equal to or less than 30 microns; see Par.[0023] wherein while silicon has a Young's Modulus of 150 GPa; The Young's modulus of the common interconnect metals aluminum, copper, and gold are 70 GPa, 120 GPa to 128 GPa, and 78 GPa, respectively).
With respect to claim 3, Gruenhagen discloses, in Figs.1-14, the semiconductor device, wherein a Young's modulus of the first metal layer is larger than a Young's modulus of the second metal layer (see Par.[0019] wherein portions of source and drain electrodes 225-226 lie in the cross section and are schematically shown by respective solid lines; gate electrode 224 may comprise a conductive layer spaced from a surface of semiconductor body 210 by a dielectric layer, and electrodes 225 and 226 may comprise doped regions of semiconductor body 210 (e.g.; silicon); see Par.[0020] wherein semiconductor die 200 further comprises a first electrically conductive layer 240 disposed on trench surface 231 and a portion of the die's second surface 212 (e.g., the drain electrode 226); layer 240 may comprise one or more metals, disposed together and/or in sub-layers; copper may be used; it may have a thickness in the range of 0.5 microns to 5 microns, or more; the thickness of layer 240 is preferably equal to or less than 30 microns; see Par.[0023] wherein while silicon has a Young's Modulus of 150 GPa; The Young's modulus of the common interconnect metals aluminum, copper, and gold are 70 GPa, 120 GPa to 128 GPa, and 78 GPa, respectively).
With respect to claim 5, Gruenhagen discloses, in Figs.1-14, the semiconductor device, wherein a thickness of the first metal layer is smaller than a thickness of the second metal layer.
With respect to claim 6, Gruenhagen discloses, in Figs.1-14, the semiconductor device, wherein a thickness of the first metal layer is smaller than a thickness of the second metal layer.
With respect to claim 7, Gruenhagen discloses, in Figs.1-14, the semiconductor device, wherein the frame convex portion of the lead frame includes a plurality of small convex portions.
With respect to claim 8, Gruenhagen discloses, in Figs.1-14, the semiconductor device, wherein the frame convex portion of the lead frame has a quadrangular pyramid shape.
With respect to claim 9, Gruenhagen discloses, in Figs.1-14, the semiconductor device, wherein a second frame convex portion having a height different from that of the frame convex portion is provided on the frame main surface of the lead frame, the semiconductor device further comprises a second semiconductor chip having a second semiconductor layer and a second electrode provided on a bottom surface of the second semiconductor layer and bonded to the second frame convex portion, the second semiconductor chip having a thickness different from that of the semiconductor chip, the second electrode of the second semiconductor chip has a second protrusion surrounding the second frame convex portion, an outer side surface of the second protrusion is flush with a side surface of the second semiconductor layer, and a height of an upper surface of the semiconductor chip is the same as a height of an upper surface of the second semiconductor chip (see Par.[0030] wherein referring to FIG. 6, a plurality of device regions 220 are manufactured on a semiconductor wafer, one of which is shown in the figure. The wafer provides the semiconductor body 210 of the die; the device regions 220 may be manufactured to provide any of the above types of power devices, including rectifiers and transistors).
With respect to claim 10, Gruenhagen discloses, in Figs.1-14, the semiconductor device, wherein a concave portion defined by an electrode main surface of the electrode on a side opposite to a surface in contact with the semiconductor layer and the protrusion is fitted to the frame convex portion of the lead frame.
With respect to claim 11, Gruenhagen discloses, in Figs.1-14, the semiconductor device, wherein a surface of the semiconductor layer (220) in contact with the electrode is flat.
With respect to claim 12, Gruenhagen discloses, in Figs.1-14, the semiconductor device, wherein a height of the frame convex portion is higher than a height of the protrusion such that the protrusion of the semiconductor chip is separated from the frame main surface of the lead frame.
With respect to claim 13, Gruenhagen discloses, in Figs.1-14, the semiconductor device, wherein the semiconductor chip is bonded to the lead frame via a bonding material.
With respect to claim 15, Gruenhagen discloses, in Figs.1-14, he semiconductor device, wherein the semiconductor chip is an IGBT, a MOSFET, or an FRD (see Par.[0030] wherein the device regions 220 may be manufactured to provide any of the above types of power devices (e.g.; IGBT), including rectifiers and transistors).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Gruenhagen in view of Okamoto (US 2024/0421049 A1).
With respect to claim 4, Gruenhagen discloses all the claimed limitations in claim 3. However, Gruenhagen does not explicitly disclose the limitations of claim 4.
Okamoto discloses, in Figs.1-28, the semiconductor device, wherein a material of the first metal layer (93/102 includes nickel and/or copper, and a material of the second metal layer (93/101) includes aluminum and/or silver (see Par.[0136] wherein the second embedded portion 93 may contain at least one among aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy and an aluminum-copper alloy).
Gruenhagen and Okamoto are analogous art because they are all directed to a semiconductor device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Gruenhagen to include Okamoto because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the first and second electrodes material in Gruenhagen by including copper first electrode and aluminum second electrode as taught by Okamoto in order to utilize the properties of copper and aluminum metals so as to provide the electrodes which offer advantages like excellent conductivity, light weight, and corrosion resistance, making them great for electrical & aerospace uses.
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818