CTNF 18/458,918 CTNF 85873 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA 3. Claim(s) 1-10, 12-15 , is/are rejected under 35 U.S.C. 102 (a1) as being anticipated by Gilroy et al., US 2006/0258120 A1 . Claims 1, 7, 12. Gilroy et al., disclose a semiconductor package (such as the one in figs. 1, 2, item 10, [0018]) comprising: -a first package level (item 12) including a first-level chip-let or intermediate interposer; -a second package level (item 20) including a first second-level chip-let and a second second-level chip-let; -wherein the first package level is direct bonded with the second package level (this limitation would read through [0018] wherein is disclosed after fabrication is complete, the contact pads 14, 22 form a plurality of direct copper bonds such that the gap between the two wafers 12, 20 is eliminated); -and wherein the first-level chip-let or intermediate interposer includes an electrical-to-optical (EO) converter electrically connected with the first second-level chip-let, an optical-to-electrical (OE) converter electrically connected with the second second-level chip-let, and an optical interconnect that connects the EO converter and the OE converter (this limitation would read through fig. 2, [0019] wherein is disclosed the electro-optic converter such as optical detector 30 is positioned between the optical coupler 28 and one or more of the intermediate contact pads 22 such that the optical detector 30 enables transfer of an electrical signal to the intermediate contact pads based on the optical signal). Claim 2. Gilroy et al., disclose the semiconductor package of claim 1, wherein the first-level chip-let is dielectric-dielectric bonded to a common insulator layer spanning across the first second-level chip-let and the second second-level chip-let, and metal-metal bonded to metal contact plugs extending through the common insulator layer (this limitation would read through fig. 2, [0019] wherein is disclosed as will be discussed in greater detail below, after fabrication is complete, the contact pads 14, 22 form a plurality of direct copper bonds such that the gap between the two wafers 12, 20 is eliminated). Claims 3, 8. Gilroy et al., disclose the semiconductor package of claims 1, 7, wherein the optical interconnect comprises a waveguide or photonic wire (this limitation would read through fig. 2, [0020] wherein is disclosed that the optical emitter 36 enables transfer of an optical signal to the waveguide 32 based on the electrical signal transported by the intermediate contact pads 22e and 22f). Claim 4. Gilroy et al., disclose the semiconductor package of claim 1, wherein the EO converter is connected to a first electromagnetic field communication structure, and the first second-level chip-let includes a second electromagnetic field communication structure (this limitation would read through fig. 2, [0020] wherein is disclosed that the optical emitter 36 enables transfer of an optical signal to the waveguide 32 based on the electrical signal transported by the intermediate contact pads 22e and 22f). Claim 5. Gilroy et al., disclose the semiconductor package of claim 4, wherein the first electromagnetic field communication structure and the second electromagnetic field communication structure are vertically aligned (this limitation would read through fig. 2, [0018] wherein is disclosed that the IC contact pads 14 are connected to an IC (not shown) on the IC wafer 12 by way of vertically extending vias 16 and horizontally extending wires or traces 18). Claim 6. Gilroy et al., disclose the semiconductor package of claim 5, wherein the first electromagnetic field communication structure and the second electromagnetic field communication structure are coils or capacitors (this limitation would read through fig. 2, [0025] wherein is disclosed that such losses include unwanted interconnect delay, resistance, capacitance, and loop inductance). Claims 9-10. Gilroy et al., disclose the semiconductor package of claim 8, further comprising a first optical via that optically connects the EO converter to the optical interconnect, and a second optical via that optically connects the optical interconnect to the OE converter. (this limitation would read through [0018] wherein is disclosed after fabrication is complete, the contact pads 14, 22 form a plurality of direct copper bonds such that the gap between the two wafers 12, 20 is eliminated); -and wherein the first-level chip-let or intermediate interposer includes an electrical-to-optical (EO) converter electrically connected with the first second-level chip-let, an optical-to-electrical (OE) converter electrically connected with the second second-level chip-let, and an optical interconnect that connects the EO converter and the OE converter (this limitation would read through fig. 2, [0019] wherein is disclosed the electro-optic converter such as optical detector 30 is positioned between the optical coupler 28 and one or more of the intermediate contact pads 22 such that the optical detector 30 enables transfer of an electrical signal to the intermediate contact pads based on the optical signal). Claim 13. Gilroy et al., disclose the semiconductor package of claim 12, wherein the first package level includes the first-level chip-let, and the intermediate interposer is vertically between the first-level chip-let and the second-level chip-let, and further comprising an optical via that through the intermediate interposer vertically between the first-level chip-let and the second-level chip-let (this limitation would read through fig. 2, [0019] wherein is disclosed the electro-optic converter such as optical detector 30 is positioned between the optical coupler 28 and one or more of the intermediate contact pads 22 such that the optical detector 30 enables transfer of an electrical signal to the intermediate contact pads based on the optical signal). Claim 14. Gilroy et al., disclose the semiconductor package of claim 12, wherein the first package level includes the first-level chip-let, the first-level chip-let is direct bonded with the intermediate interposer, and the second-level chip-let is direct bonded with the intermediate interposer (this limitation would read through fig. 2, [0019] wherein is disclosed the electro-optic converter such as optical detector 30 is positioned between the optical coupler 28 and one or more of the intermediate contact pads 22 such that the optical detector 30 enables transfer of an electrical signal to the intermediate contact pads based on the optical signal). Claim 15. Gilroy et al., disclose the semiconductor package of claim 12, wherein the second-level chip-let includes a plurality of sub-chip-lets, and the optical via extends through one or more of the plurality of sub-chip-lets (this limitation would read through fig. 2, [0019] wherein is disclosed the electro-optic converter such as optical detector 30 is positioned between the optical coupler 28 and one or more of the intermediate contact pads 22 such that the optical detector 30 enables transfer of an electrical signal to the intermediate contact pads based on the optical signal) . Claim Rejections - 35 USC § 103 07-20-aia AIA 4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or non-obviousness. 07-21-aia AIA 5. Claim (s) 11 , is/are rejected under 35 U.S.C. 103 as being unpatentable over Gilroy et al., US 2006/0258120 A1, in view of Zhai, US 2021/0125967 A1 . Claim 11. Gilroy et al., disclose the semiconductor package of claim 7, above. Gilroy appears to not specify “wherein the first-level chip-let is oxide-oxide bonded to a common insulator layer spanning across the first second-level chip-let and the second second-level chip-let”. However, Zhai [0019], discloses while hybrid bonding with metal-metal and oxide-oxide bonding can achieve a high connection density. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic component package of Gilroy et al., so that the first-level chip-let is oxide-oxide bonded to a common insulator layer spanning across the first second-level chip- let and the second second-level chip-let as taught by Zhai to provide superior thermal management (CTE matching), excellent electrical isolation, high reliability with reduced stress, enabling finer pitches for 3D integration, better power integrity, and sealing for MEMS/sensors, overcoming limitations of traditional solder/wire bonding for advanced, compact devices. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00. 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For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/458,918 Page 2 Art Unit: 2899 Application/Control Number: 18/458,918 Page 3 Art Unit: 2899 Application/Control Number: 18/458,918 Page 4 Art Unit: 2899 Application/Control Number: 18/458,918 Page 5 Art Unit: 2899 Application/Control Number: 18/458,918 Page 6 Art Unit: 2899 Application/Control Number: 18/458,918 Page 7 Art Unit: 2899