DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-10 and 20, in the reply filed on January 2, 2026 is acknowledged. Therefore, claims 1-10 and 20 are presented for examination.
Claim Objections
Claim 1 is objected to because of the following informalities:
On line 5, “the first via passes through the lateral contact” should be amended to better clarify the claimed invention, because Applicants originally disclosed in Fig. 1B that the first via 126a is physically and laterally contacted with an edge of the lateral contact 114 rather than the first via passing through the lateral contact; this is akin to a situation where two perpendicular lines constituting the letter “T” do not pass through each other, while they contact each other at one point.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5, 7-8 and 20 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Kim et al. (US 2023/0095830, Foreign Priority: Sep. 27, 2021 (KR); hereinafter Kim).
Regarding claim 1, Kim disclose for a semiconductor device comprising that
a first source/drain region (first source/drain pattern SD1, Fig. 4D) connected to a back end of line (BEOL) (first metal layer M1, Fig. 4D), because “the first metal layer M1 and metal layers (e.g., M2, M3, M4, etc.) on the first metal layer M1 may constitute a back-end-of-line (BEOL) layer of a semiconductor device” (emphasis added, [0098]) through a first contact (connection part CNP or pad part PDP of first active contact AC1, Fig. 4D) and a first via (first upper via UVI1, Fig. 4D); and
a second source/drain region (second source/drain pattern SD2, Fig. 4D) connected to the BEOL (M1, Fig. 4D) through a second contact (connection part CNP of second active contact AC2, Fig. 4D), a lateral contact (pad part PDP of second active contact AC2, Fig. 4D) and a second via (second upper via UVI2, Fig. 4D),
wherein the first via (UVI1, Fig. 4D) passes through the lateral contact (PDP of AC2, Fig. 4D), and wherein the first source/drain region (SD1, Fig. 4D) is formed over the second source/drain region (SD2, Fig. 4D), because Applicants do not specifically claim what geometrical orientation the claimed device has and/or where the back end of line (BEOL) is positioned, when the device by Kim is considered in an inverted orientation as shown in the attached Fig. 4D of Kim below, the first source/drain pattern SD1 is positioned over the second source/drain pattern SD2 and the first upper via UVI1 passes through the pad part of the second active contact AC2 to contact with the first metal layer M1 (see Fig. 4D below).
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Regarding claim 3, Kim further discloses for the semiconductor device of claim 1 that a first transistor (first active region AR1, Fig. 4D) stacked over a second transistor (second active region AR2, see Fig. 4D above), wherein the first and second (SD1 and SD2, Fig. 4D) source/drain regions are located on the first and the second transistors (AR1 and AR2, Fig. 4D), respectively.
Regarding Claim 5, Kim further discloses for the semiconductor device of claim 1 that a first isolation layer (third interlayer dielectric layer 130, Fig. 4D) covering the first via (UVI1, Fig. 4D), wherein a portion of the first isolation layer (portion of 130, Fig. 4D) is connected to the lateral contact (PDP of AC2, Fig. 4D), because the third interlayer dielectric layer 130 by Kim surrounds the second active contact AC2 (Fig. 4D).
Regarding claim 7, Kim further discloses for the semiconductor device of claim 1 that a gate via (gate contact GC, Fig. 4B) connecting a gate region (gate electrode GE, Fig. 4A) to the BEOL (M1, Fig. 4A).
Regarding claim 8, Kim further discloses for the semiconductor device of claim 7 that a location of the second via (UVI2, Fig. 4D) is offset from a centerline of the second source/drain region (centerline of SD2, Fig. 4D) away from the gate region (GE, Fig. 4A), because the second source/drain pattern SD2 by Kim is offset from the gate electrode GE (Fig. 4A).
Regarding claim 20, Kim further discloses for a semiconductor device comprising that a source/drain via (second upper via UVI2, Fig. 4D) connecting a source/drain region (second source/drain pattern SD2, Fig. 4D) to a back end of line (BEOL) (first metal layer M1, Fig. 4D), because “the first metal layer M1 and metal layers (e.g., M2, M3, M4, etc.) on the first metal layer M1 may constitute a back-end-of-line (BEOL) layer of a semiconductor device” (emphasis added, [0098]); and
a gate via (gate contact GC, Fig. 4B) connecting a gate region (gate electrode GE, Fig. 4B) to the BEOL (M1, Fig. 4B),
wherein the gate via (GC, Fig. 4B) and the source/drain via (UVI2, Fig. 4D) are isolated from direct contact with a lateral contact (first active contact AC1, Fig. 4D) through a first and a second dielectric isolation layer (second and third interlayer dielectric layer 120 and 130, Fig. 4D) formed over the source/drain via (UVI2, Fig. 4D) and the gate via (GC, Fig. 4B), respectively, because Applicants do not specifically claim what geometrical orientation the claimed device has and/or where the back end of line (BEOL) is positioned, when the device by Kim is considered in an inverted orientation (see attached Fig. 4D above), the second and third interlayer dielectric layer 120 and 130, which correspond to the first and second dielectric isolation layer in the claimed invention, are positioned over the second source/drain pattern SD2 and the gate contact GC (Figs. 4B, 4D).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over by Kim et al. (US 2023/0095830, Foreign Priority: Sep. 27, 2021 (KR); hereinafter Kim) in view of Zhang et al. (US 2020/0381300, hereinafter Zhang).
Regarding claim 2, Kim differs from the claimed invention by not showing that the lateral contact is located above the first and second source/drain regions.
However, Zhang discloses for a vertically stacked field-effect transistors that the stacked device includes that the top source/drain region 134 and the bottom source/drain region 206 (Fig. 12), which correspond to the first and second source/drain region in the claimed invention, respectively, and the metal contact 702 is connected with the bottom source/drain region 206, and therefore, the metal contact 702 (Fig. 12) corresponds to the second contact in the claimed invention; a metal contact is formed in the contact trench 1202 directly on the metal contact 702 (Fig. 12), therefore, an upper layer of the buried Vdd power line 1302 corresponds to the lateral contact in the claimed invention; in this case, the buried Vdd power line 1302 is located above the top and bottom source/drain regions 134 and 206 (Fig. 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertically stacked transistor to include a laterally extended contact and it can be located above the upper and lower source/drain regions of the vertically stacked transistor, as an obvious matter of design choice to optimize device performance of the semiconductor device.
Regarding claim 4, Kim differs from the claimed invention by now showing that the second contact further comprises a horizontally extended portion over the second source/drain region; and a vertically extended portion connecting the horizontally extended portion to the lateral contact.
However, Zhang further discloses that the second contact (702, Fig. 12) further comprises a horizontally extended portion (lower/wider portion of 702, see attached Fig. 12 below) over the second source/drain region (206, Fig. 12), because the metal contact 702 by Zhang has a trapezoidal shape, and therefore, a lower portion of the metal contact 702 is horizontally extended and wider than a upper portion; and a vertically extended portion (vertically portion of 702, see attached Fig. 12 below) connecting the horizontally extended portion to the lateral contact (1302, Fig. 13). Examiner notes that the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, and therefore, a wide portion of the metal contact 702 above the bottom source/drain region 206 by Zhang can be selected as the claimed horizontally extended portion as shown in the attached Fig. 12 of Zhang below.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertically stacked transistor to include a metal contact or via having horizontally and vertically extended portion above the lower source/drain region of the vertically stacked transistor, as an obvious matter of design choice to optimize device performance of the semiconductor device.
Allowable Subject Matter
Claims 6 and 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/WOO K LEE/Examiner, Art Unit 2815