DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election of Invention I encompassing claims 1-12 was made without traverse in the reply filed on 02/13/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pagaila et al. (US 2012/0056312 A1 hereinafter referred to as “Pagaila ‘2”).
With respect to claim 1, Pagaila ‘2 discloses, in Figs.1-12, a package, comprising: first (124b) and second (124d) dies including first (124a) and second (124c) diodes, respectively (see Par.[0042] wherein each semiconductor die 124 has a back surface 128 and an active surface 130 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die; for example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 130 to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit); first (132) and second (132) metal contacts coupled to bottom surfaces of the first (124b) and second (124d) dies, respectively, the first (132) and second (132) metal contacts exposed to a bottom surface of the package (see Par.[0043] wherein an electrically conductive layer 132 is formed over active surface 130 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material); an isolation layer (154/238) between the first (124b) and second (124d) dies and between the first (132) and second (132) metal contacts (see Par.[0052]-[0053] wherein an encapsulant or molding compound 154 is non-conductive material deposited within cavity 150 around the stacked semiconductor die 124 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator; encapsulant 154 using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation; the insulating layer 156 contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties; see Par.[0073]-[0074] wherein encapsulant 238 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler; encapsulant 238 using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation); a metal layer (158/242) coupled to top surfaces of the first (124b) and second (124d) dies; and a mold compound (160/244) covering the first (124b) and second (124d) dies and the metal layer (158) (see Par.[0054]-[0055] wherein conductive layer 158 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material; one portion of conductive layer 158 is electrically connected to contact pads 132 of semiconductor die 124b and 124d; another portion of conductive layer 158 is electrically connected to conductive TSV 148; an insulating or passivation layer 160 is formed over insulating layer 156 and conductive layer 158 using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation; the insulating layer 160 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties; see Par.[0069] wherein encapsulant 224 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler).
With respect to claim 2, Pagaila ‘2 discloses, in Figs.1-12, the package, further comprising third (132) and fourth (132) metal contacts exposed to the top surfaces of the first (124b) and second (124d) dies, wherein the third (132) and fourth (132) metal contacts are positioned under the metal layer (158) (see Fig.12, wherein upper metal 132 contact metal 158; see Par.[0054]-[0055] wherein conductive layer 158 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material; one portion of conductive layer 158 is electrically connected to contact pads 132 of semiconductor die 124b and 124d; another portion of conductive layer 158 is electrically connected to conductive TSV 148; an insulating or passivation layer 160 is formed over insulating layer 156 and conductive layer 158 using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation; the insulating layer 160 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties).
With respect to claim 3, Pagaila ‘2 discloses, in Figs.1-12, the package, wherein the isolation layer (238) comprises parylene or resin (see Par.[0052]-[0053] wherein an encapsulant or molding compound 154 is non-conductive material deposited within cavity 150 around the stacked semiconductor die 124 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator; encapsulant 154 using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation; the insulating layer 156 contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties; see Par.[0073]-[0074] wherein encapsulant 238 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler; encapsulant 238 using PVD, CVD, 146printing, spin coating, spray coating, sintering or thermal oxidation).
With respect to claim 6, Pagaila ‘2 discloses, in Figs.1-12, the package, wherein the metal layer (158) is a rectangular prism (see Figs.11-12).
With respect to claim 7, Pagaila ‘2 discloses, in Figs.1-12, the package, wherein the first and second metal contacts (132) are rectangular prisms (see Figs.11-12).
Claims 1-10, 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pagaila (US 2012/0217644 A1).
With respect to claim 1, Pagaila discloses, in Figs.1-10b, a package, comprising: first (124) and second (124) dies including first (124) and second (124) diodes, respectively (see Fig.7, wherein plurality of stack of dies 124 (including chip and diodes) separated by wafer area or saw streets; see Par.[0040] wherein each semiconductor die 124 has a back surface 128 and active surface 130 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die; for example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 130 to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit); first (132) and second (132) metal contacts coupled to bottom surfaces of the first (124) and second (124) dies, respectively, the first (132) and second (132) metal contacts exposed to a bottom surface of the package (see Par.[0041] wherein conductive layer 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material; conductive layer 132 operates as contact pads electrically connected to the circuits on active surface 130; contact pads 132 can be disposed side-by-side a first distance from the edge of semiconductor die 124); an isolation layer (146) between the first and second dies (124) and between the first and second metal contacts (132) (see Par.[0046] wherein encapsulant 146 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler); a metal layer (160, 166) coupled to top surfaces of the first and second dies (124) (see Par.[0053]-[0058] wherein an electrically conductive layer or RDL 160 is formed over back surface 128 of semiconductor die 124 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating; conductive layer 160 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material; conductive layer 160 is electrically connected to conductive THVs 152); and a mold compound (168) covering the first and second dies (124) and the metal layer (132) (see Par.[0057] wherein an encapsulant or molding compound 168 is deposited over semiconductor die 124 and substrate 164 in using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator; encapsulant 168 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler).
With respect to claim 2, Pagaila discloses, in Figs.1-10b, the package, further comprising third and fourth metal contacts (132) exposed to the top surfaces of the first and second dies (124), wherein the third and fourth metal contacts (132) are positioned under the metal layer (160, 166) (see Fig.7, wherein metals 132 contacts metals 166 or 160 at the surfaces; see Par.[0041] wherein conductive layer 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material; conductive layer 132 operates as contact pads electrically connected to the circuits on active surface 130; contact pads 132 can be disposed side-by-side a first distance from the edge of semiconductor die 124).
With respect to claim 3, Pagaila discloses, in Figs.1-10b, the package, wherein the isolation layer (146) comprises parylene or resin (see Par.[0046] wherein encapsulant 146 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler).
With respect to claim 4, Pagaila discloses, in Figs.1-10b, the package, wherein a distance between the first and second metal contacts ranges between 5 microns and 10 microns (see Figs.4i wherein distances between first and second metal contacts includes two vias 148; see Par.[0049] wherein conductive THVs 152 follow the contour of sidewalls 150 of vias 148 with a thickness of 3 micrometers (.mu.m); as such the distance between metals is more than the width of two vias (i.e.; 6 microns)).
With respect to claim 5, Pagaila discloses, in Figs.1-10b, the package, wherein: the isolation layer (146) includes a surface exposed from the package; and the isolation layer contacts side surfaces of the first and second dies, and the first and second metal contacts, and a portion of the metal layer (see Fig.4i).
With respect to claim 6, Pagaila discloses, in Figs.1-10b, the package, wherein the metal layer is a rectangular prism (see for example, Fig.4i for rectangular shape of metal layer and metal contacts).
With respect to claim 7, Pagaila discloses, in Figs.1-10b, the package, wherein the first and second metal contacts are rectangular prisms (see for example, Fig.4i for rectangular shape of metal layer and metal contacts).
With respect to claim 8, Pagaila discloses, in Figs.1-10b, a package, comprising: first and second dies (124) including first and second diodes (124), respectively (see Fig.7, wherein plurality of stack of dies 124 (including chip and diodes) separated by wafer area or saw streets; see Par.[0040] wherein each semiconductor die 124 has a back surface 128 and active surface 130 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die; for example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 130 to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit); first and second metal contacts (132) coupled to bottom surfaces of the first and second dies (124), respectively, the first and second metal contacts (132) exposed to a bottom surface of the package; third and fourth metal contacts (132) exposed to top surfaces of the first and second dies (132), respectively (see Par.[0041] wherein conductive layer 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material; conductive layer 132 operates as contact pads electrically connected to the circuits on active surface 130; contact pads 132 can be disposed side-by-side a first distance from the edge of semiconductor die 124); isolation material (146) between the first and second dies (124), between the first and second metal contacts (132), and between the third and fourth metal contacts (132) (see Par.[0046] wherein encapsulant 146 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler); a flat metal layer (160) coupled to the top surfaces of the first and second dies (124) (see Par.[0053] wherein an electrically conductive layer or RDL 160 is formed over back surface 128 of semiconductor die 124 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating; conductive layer 160 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 160 is electrically connected to conductive THVs 152); and a mold compound (168) covering the first and second dies (124) and the flat metal layer (160), wherein the first and second metal contacts (132) are spaced between 5 microns and 10 microns apart (see Par.[0057] wherein an encapsulant or molding compound 168 is deposited over semiconductor die 124 and substrate 164 in using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator; encapsulant 168 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler; see Figs.4i wherein distances between first and second metal contacts includes two vias 148; see Par.[0049] wherein conductive THVs 152 follow the contour of sidewalls 150 of vias 148 with a thickness of 3 micrometers (.mu.m); as such the distance between metals is more than the width of two vias (i.e.; 6 microns)).
With respect to claim 9, Pagaila discloses, in Figs.1-10b, the package, wherein the metal layer is a rectangular prism (see for example, Fig.4i for rectangular shape of metal layer and metal contacts).
With respect to claim 10, Pagaila discloses, in Figs.1-10b, the package, wherein the first and second metal contacts are rectangular prisms (see for example, Fig.4i for rectangular shape of metal layer and metal contacts).
With respect to claim 12, Pagaila discloses, in Figs.1-10b, the package, wherein the isolation material (146) comprises parylene or resin (see Par.[0046] wherein encapsulant 146 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Pagaila.
With respect to claim 11, Pagaila discloses, in Figs.1-10b, the package, wherein the flat metal layer (160) has a thickness. However, Paigala does not explicitly teach that the package, wherein the flat metal layer has a thickness ranging from 1 micron to 100 microns.
Even though Paigala does not disclose the flat metal layer has a thickness ranging from 1 micron to 100 microns, the said range is predictable by simple engineering optimization motivated by a design choice, such as, optimization of chip size reduction. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818